35 lines
838 B
C
35 lines
838 B
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2014 - 2015 Xilinx, Inc.
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* Michal Simek <michal.simek@xilinx.com>
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* (This file derived from arch/arm/cpu/armv8/zynqmp/cpu.c)
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*
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* Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved.
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*/
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#include <common.h>
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#include <asm/system.h>
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#include <asm/armv8/mmu.h>
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/* size: IO + NR_DRAM_BANKS + terminator */
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struct mm_region tegra_mem_map[1 + CONFIG_NR_DRAM_BANKS + 1] = {
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{
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.virt = 0x0UL,
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.phys = 0x0UL,
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.size = 0x80000000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE |
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PTE_BLOCK_PXN | PTE_BLOCK_UXN
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}, {
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.virt = 0x80000000UL,
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.phys = 0x80000000UL,
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.size = 0x80000000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
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PTE_BLOCK_INNER_SHARE
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}, {
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/* List terminator */
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0,
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}
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};
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struct mm_region *mem_map = tegra_mem_map;
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