73 lines
1.1 KiB
C
73 lines
1.1 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2017 Andes Technology Corporation
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* Rick Chen, Andes Technology Corporation <rick@andestech.com>
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*/
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#include <common.h>
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void invalidate_icache_all(void)
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{
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asm volatile ("fence.i" ::: "memory");
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}
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void flush_dcache_all(void)
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{
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asm volatile ("fence" :::"memory");
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}
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void flush_dcache_range(unsigned long start, unsigned long end)
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{
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flush_dcache_all();
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}
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void invalidate_icache_range(unsigned long start, unsigned long end)
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{
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/*
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* RISC-V does not have an instruction for invalidating parts of the
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* instruction cache. Invalidate all of it instead.
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*/
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invalidate_icache_all();
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}
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void invalidate_dcache_range(unsigned long start, unsigned long end)
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{
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flush_dcache_all();
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}
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void cache_flush(void)
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{
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invalidate_icache_all();
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flush_dcache_all();
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}
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void flush_cache(unsigned long addr, unsigned long size)
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{
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invalidate_icache_all();
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flush_dcache_all();
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}
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__weak void icache_enable(void)
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{
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}
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__weak void icache_disable(void)
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{
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}
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__weak int icache_status(void)
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{
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return 0;
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}
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__weak void dcache_enable(void)
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{
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}
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__weak void dcache_disable(void)
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{
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}
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__weak int dcache_status(void)
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{
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return 0;
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}
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