377 lines
9.1 KiB
C
377 lines
9.1 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
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*/
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#include <common.h>
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#include <dm.h>
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#include <errno.h>
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#include <fdtdec.h>
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#include <malloc.h>
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#include <asm/io.h>
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#include <asm/irq.h>
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#include <asm/pci.h>
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#include <asm/pirq_routing.h>
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#include <asm/tables.h>
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DECLARE_GLOBAL_DATA_PTR;
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/**
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* pirq_reg_to_linkno() - Convert a PIRQ routing register offset to link number
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*
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* @priv: IRQ router driver's priv data
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* @reg: PIRQ routing register offset from the base address
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* @return: PIRQ link number (0 for PIRQA, 1 for PIRQB, etc)
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*/
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static inline int pirq_reg_to_linkno(struct irq_router *priv, int reg)
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{
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int linkno = 0;
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if (priv->has_regmap) {
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struct pirq_regmap *map = priv->regmap;
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int i;
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for (i = 0; i < priv->link_num; i++) {
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if (reg - priv->link_base == map->offset) {
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linkno = map->link;
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break;
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}
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map++;
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}
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} else {
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linkno = reg - priv->link_base;
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}
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return linkno;
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}
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/**
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* pirq_linkno_to_reg() - Convert a PIRQ link number to routing register offset
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*
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* @priv: IRQ router driver's priv data
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* @linkno: PIRQ link number (0 for PIRQA, 1 for PIRQB, etc)
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* @return: PIRQ routing register offset from the base address
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*/
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static inline int pirq_linkno_to_reg(struct irq_router *priv, int linkno)
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{
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int reg = 0;
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if (priv->has_regmap) {
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struct pirq_regmap *map = priv->regmap;
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int i;
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for (i = 0; i < priv->link_num; i++) {
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if (linkno == map->link) {
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reg = map->offset + priv->link_base;
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break;
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}
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map++;
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}
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} else {
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reg = linkno + priv->link_base;
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}
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return reg;
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}
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bool pirq_check_irq_routed(struct udevice *dev, int link, u8 irq)
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{
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struct irq_router *priv = dev_get_priv(dev);
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u8 pirq;
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if (priv->config == PIRQ_VIA_PCI)
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dm_pci_read_config8(dev->parent,
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pirq_linkno_to_reg(priv, link), &pirq);
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else
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pirq = readb((uintptr_t)priv->ibase +
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pirq_linkno_to_reg(priv, link));
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pirq &= 0xf;
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/* IRQ# 0/1/2/8/13 are reserved */
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if (pirq < 3 || pirq == 8 || pirq == 13)
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return false;
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return pirq == irq ? true : false;
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}
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int pirq_translate_link(struct udevice *dev, int link)
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{
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struct irq_router *priv = dev_get_priv(dev);
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return pirq_reg_to_linkno(priv, link);
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}
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void pirq_assign_irq(struct udevice *dev, int link, u8 irq)
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{
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struct irq_router *priv = dev_get_priv(dev);
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/* IRQ# 0/1/2/8/13 are reserved */
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if (irq < 3 || irq == 8 || irq == 13)
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return;
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if (priv->config == PIRQ_VIA_PCI)
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dm_pci_write_config8(dev->parent,
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pirq_linkno_to_reg(priv, link), irq);
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else
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writeb(irq, (uintptr_t)priv->ibase +
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pirq_linkno_to_reg(priv, link));
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}
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static struct irq_info *check_dup_entry(struct irq_info *slot_base,
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int entry_num, int bus, int device)
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{
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struct irq_info *slot = slot_base;
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int i;
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for (i = 0; i < entry_num; i++) {
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if (slot->bus == bus && slot->devfn == (device << 3))
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break;
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slot++;
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}
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return (i == entry_num) ? NULL : slot;
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}
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static inline void fill_irq_info(struct irq_router *priv, struct irq_info *slot,
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int bus, int device, int pin, int pirq)
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{
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slot->bus = bus;
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slot->devfn = (device << 3) | 0;
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slot->irq[pin - 1].link = pirq_linkno_to_reg(priv, pirq);
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slot->irq[pin - 1].bitmap = priv->irq_mask;
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}
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static int create_pirq_routing_table(struct udevice *dev)
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{
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struct irq_router *priv = dev_get_priv(dev);
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const void *blob = gd->fdt_blob;
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int node;
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int len, count;
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const u32 *cell;
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struct pirq_regmap *map;
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struct irq_routing_table *rt;
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struct irq_info *slot, *slot_base;
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int irq_entries = 0;
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int i;
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int ret;
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node = dev_of_offset(dev);
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/* extract the bdf from fdt_pci_addr */
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priv->bdf = dm_pci_get_bdf(dev->parent);
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ret = fdt_stringlist_search(blob, node, "intel,pirq-config", "pci");
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if (!ret) {
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priv->config = PIRQ_VIA_PCI;
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} else {
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ret = fdt_stringlist_search(blob, node, "intel,pirq-config",
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"ibase");
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if (!ret)
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priv->config = PIRQ_VIA_IBASE;
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else
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return -EINVAL;
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}
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cell = fdt_getprop(blob, node, "intel,pirq-link", &len);
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if (!cell || len != 8)
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return -EINVAL;
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priv->link_base = fdt_addr_to_cpu(cell[0]);
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priv->link_num = fdt_addr_to_cpu(cell[1]);
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if (priv->link_num > CONFIG_MAX_PIRQ_LINKS) {
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debug("Limiting supported PIRQ link number from %d to %d\n",
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priv->link_num, CONFIG_MAX_PIRQ_LINKS);
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priv->link_num = CONFIG_MAX_PIRQ_LINKS;
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}
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cell = fdt_getprop(blob, node, "intel,pirq-regmap", &len);
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if (cell) {
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if (len % sizeof(struct pirq_regmap))
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return -EINVAL;
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count = len / sizeof(struct pirq_regmap);
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if (count < priv->link_num) {
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printf("Number of pirq-regmap entires is wrong\n");
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return -EINVAL;
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}
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count = priv->link_num;
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priv->regmap = calloc(count, sizeof(struct pirq_regmap));
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if (!priv->regmap)
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return -ENOMEM;
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priv->has_regmap = true;
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map = priv->regmap;
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for (i = 0; i < count; i++) {
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map->link = fdt_addr_to_cpu(cell[0]);
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map->offset = fdt_addr_to_cpu(cell[1]);
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cell += sizeof(struct pirq_regmap) / sizeof(u32);
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map++;
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}
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}
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priv->irq_mask = fdtdec_get_int(blob, node,
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"intel,pirq-mask", PIRQ_BITMAP);
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if (IS_ENABLED(CONFIG_GENERATE_ACPI_TABLE)) {
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/* Reserve IRQ9 for SCI */
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priv->irq_mask &= ~(1 << 9);
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}
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if (priv->config == PIRQ_VIA_IBASE) {
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int ibase_off;
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ibase_off = fdtdec_get_int(blob, node, "intel,ibase-offset", 0);
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if (!ibase_off)
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return -EINVAL;
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/*
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* Here we assume that the IBASE register has already been
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* properly configured by U-Boot before.
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*
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* By 'valid' we mean:
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* 1) a valid memory space carved within system memory space
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* assigned to IBASE register block.
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* 2) memory range decoding is enabled.
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* Hence we don't do any santify test here.
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*/
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dm_pci_read_config32(dev->parent, ibase_off, &priv->ibase);
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priv->ibase &= ~0xf;
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}
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priv->actl_8bit = fdtdec_get_bool(blob, node, "intel,actl-8bit");
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priv->actl_addr = fdtdec_get_int(blob, node, "intel,actl-addr", 0);
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cell = fdt_getprop(blob, node, "intel,pirq-routing", &len);
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if (!cell || len % sizeof(struct pirq_routing))
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return -EINVAL;
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count = len / sizeof(struct pirq_routing);
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rt = calloc(1, sizeof(struct irq_routing_table));
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if (!rt)
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return -ENOMEM;
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/* Populate the PIRQ table fields */
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rt->signature = PIRQ_SIGNATURE;
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rt->version = PIRQ_VERSION;
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rt->rtr_bus = PCI_BUS(priv->bdf);
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rt->rtr_devfn = (PCI_DEV(priv->bdf) << 3) | PCI_FUNC(priv->bdf);
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rt->rtr_vendor = PCI_VENDOR_ID_INTEL;
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rt->rtr_device = PCI_DEVICE_ID_INTEL_ICH7_31;
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slot_base = rt->slots;
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/* Now fill in the irq_info entries in the PIRQ table */
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for (i = 0; i < count;
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i++, cell += sizeof(struct pirq_routing) / sizeof(u32)) {
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struct pirq_routing pr;
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pr.bdf = fdt_addr_to_cpu(cell[0]);
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pr.pin = fdt_addr_to_cpu(cell[1]);
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pr.pirq = fdt_addr_to_cpu(cell[2]);
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debug("irq_info %d: b.d.f %x.%x.%x INT%c PIRQ%c\n",
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i, PCI_BUS(pr.bdf), PCI_DEV(pr.bdf),
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PCI_FUNC(pr.bdf), 'A' + pr.pin - 1,
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'A' + pr.pirq);
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slot = check_dup_entry(slot_base, irq_entries,
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PCI_BUS(pr.bdf), PCI_DEV(pr.bdf));
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if (slot) {
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debug("found entry for bus %d device %d, ",
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PCI_BUS(pr.bdf), PCI_DEV(pr.bdf));
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if (slot->irq[pr.pin - 1].link) {
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debug("skipping\n");
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/*
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* Sanity test on the routed PIRQ pin
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*
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* If they don't match, show a warning to tell
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* there might be something wrong with the PIRQ
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* routing information in the device tree.
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*/
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if (slot->irq[pr.pin - 1].link !=
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pirq_linkno_to_reg(priv, pr.pirq))
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debug("WARNING: Inconsistent PIRQ routing information\n");
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continue;
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}
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} else {
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slot = slot_base + irq_entries++;
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}
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debug("writing INT%c\n", 'A' + pr.pin - 1);
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fill_irq_info(priv, slot, PCI_BUS(pr.bdf), PCI_DEV(pr.bdf),
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pr.pin, pr.pirq);
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}
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rt->size = irq_entries * sizeof(struct irq_info) + 32;
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/* Fix up the table checksum */
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rt->checksum = table_compute_checksum(rt, rt->size);
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gd->arch.pirq_routing_table = rt;
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return 0;
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}
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static void irq_enable_sci(struct udevice *dev)
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{
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struct irq_router *priv = dev_get_priv(dev);
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if (priv->actl_8bit) {
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/* Bit7 must be turned on to enable ACPI */
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dm_pci_write_config8(dev->parent, priv->actl_addr, 0x80);
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} else {
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/* Write 0 to enable SCI on IRQ9 */
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if (priv->config == PIRQ_VIA_PCI)
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dm_pci_write_config32(dev->parent, priv->actl_addr, 0);
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else
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writel(0, (uintptr_t)priv->ibase + priv->actl_addr);
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}
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}
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int irq_router_probe(struct udevice *dev)
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{
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int ret;
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ret = create_pirq_routing_table(dev);
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if (ret) {
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debug("Failed to create pirq routing table\n");
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return ret;
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}
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/* Route PIRQ */
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pirq_route_irqs(dev, gd->arch.pirq_routing_table->slots,
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get_irq_slot_count(gd->arch.pirq_routing_table));
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if (IS_ENABLED(CONFIG_GENERATE_ACPI_TABLE))
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irq_enable_sci(dev);
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return 0;
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}
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ulong write_pirq_routing_table(ulong addr)
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{
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if (!gd->arch.pirq_routing_table)
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return addr;
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return copy_pirq_routing_table(addr, gd->arch.pirq_routing_table);
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}
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static const struct udevice_id irq_router_ids[] = {
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{ .compatible = "intel,irq-router" },
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{ }
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};
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U_BOOT_DRIVER(irq_router_drv) = {
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.name = "intel_irq",
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.id = UCLASS_IRQ,
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.of_match = irq_router_ids,
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.probe = irq_router_probe,
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.priv_auto_alloc_size = sizeof(struct irq_router),
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};
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UCLASS_DRIVER(irq) = {
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.id = UCLASS_IRQ,
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.name = "irq",
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};
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