258 lines
6.2 KiB
C
258 lines
6.2 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* From coreboot src/southbridge/intel/bd82x6x/mrccache.c
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*
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* Copyright (C) 2014 Google Inc.
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* Copyright (C) 2015 Bin Meng <bmeng.cn@gmail.com>
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*/
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#include <common.h>
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#include <dm.h>
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#include <errno.h>
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#include <fdtdec.h>
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#include <net.h>
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#include <spi.h>
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#include <spi_flash.h>
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#include <asm/mrccache.h>
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DECLARE_GLOBAL_DATA_PTR;
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static struct mrc_data_container *next_mrc_block(
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struct mrc_data_container *cache)
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{
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/* MRC data blocks are aligned within the region */
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u32 mrc_size = sizeof(*cache) + cache->data_size;
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u8 *region_ptr = (u8 *)cache;
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if (mrc_size & (MRC_DATA_ALIGN - 1UL)) {
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mrc_size &= ~(MRC_DATA_ALIGN - 1UL);
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mrc_size += MRC_DATA_ALIGN;
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}
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region_ptr += mrc_size;
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return (struct mrc_data_container *)region_ptr;
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}
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static int is_mrc_cache(struct mrc_data_container *cache)
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{
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return cache && (cache->signature == MRC_DATA_SIGNATURE);
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}
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struct mrc_data_container *mrccache_find_current(struct mrc_region *entry)
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{
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struct mrc_data_container *cache, *next;
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ulong base_addr, end_addr;
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uint id;
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base_addr = entry->base + entry->offset;
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end_addr = base_addr + entry->length;
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cache = NULL;
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/* Search for the last filled entry in the region */
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for (id = 0, next = (struct mrc_data_container *)base_addr;
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is_mrc_cache(next);
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id++) {
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cache = next;
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next = next_mrc_block(next);
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if ((ulong)next >= end_addr)
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break;
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}
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if (id-- == 0) {
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debug("%s: No valid MRC cache found.\n", __func__);
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return NULL;
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}
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/* Verify checksum */
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if (cache->checksum != compute_ip_checksum(cache->data,
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cache->data_size)) {
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printf("%s: MRC cache checksum mismatch\n", __func__);
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return NULL;
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}
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debug("%s: picked entry %u from cache block\n", __func__, id);
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return cache;
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}
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/**
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* find_next_mrc_cache() - get next cache entry
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*
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* @entry: MRC cache flash area
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* @cache: Entry to start from
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*
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* @return next cache entry if found, NULL if we got to the end
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*/
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static struct mrc_data_container *find_next_mrc_cache(struct mrc_region *entry,
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struct mrc_data_container *cache)
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{
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ulong base_addr, end_addr;
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base_addr = entry->base + entry->offset;
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end_addr = base_addr + entry->length;
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cache = next_mrc_block(cache);
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if ((ulong)cache >= end_addr) {
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/* Crossed the boundary */
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cache = NULL;
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debug("%s: no available entries found\n", __func__);
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} else {
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debug("%s: picked next entry from cache block at %p\n",
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__func__, cache);
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}
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return cache;
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}
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int mrccache_update(struct udevice *sf, struct mrc_region *entry,
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struct mrc_data_container *cur)
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{
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struct mrc_data_container *cache;
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ulong offset;
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ulong base_addr;
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int ret;
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if (!is_mrc_cache(cur))
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return -EINVAL;
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/* Find the last used block */
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base_addr = entry->base + entry->offset;
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debug("Updating MRC cache data\n");
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cache = mrccache_find_current(entry);
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if (cache && (cache->data_size == cur->data_size) &&
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(!memcmp(cache, cur, cache->data_size + sizeof(*cur)))) {
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debug("MRC data in flash is up to date. No update\n");
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return -EEXIST;
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}
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/* Move to the next block, which will be the first unused block */
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if (cache)
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cache = find_next_mrc_cache(entry, cache);
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/*
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* If we have got to the end, erase the entire mrc-cache area and start
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* again at block 0.
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*/
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if (!cache) {
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debug("Erasing the MRC cache region of %x bytes at %x\n",
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entry->length, entry->offset);
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ret = spi_flash_erase_dm(sf, entry->offset, entry->length);
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if (ret) {
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debug("Failed to erase flash region\n");
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return ret;
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}
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cache = (struct mrc_data_container *)base_addr;
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}
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/* Write the data out */
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offset = (ulong)cache - base_addr + entry->offset;
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debug("Write MRC cache update to flash at %lx\n", offset);
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ret = spi_flash_write_dm(sf, offset, cur->data_size + sizeof(*cur),
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cur);
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if (ret) {
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debug("Failed to write to SPI flash\n");
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return ret;
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}
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return 0;
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}
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int mrccache_reserve(void)
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{
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struct mrc_data_container *cache;
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u16 checksum;
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if (!gd->arch.mrc_output_len)
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return 0;
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/* adjust stack pointer to store pure cache data plus the header */
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gd->start_addr_sp -= (gd->arch.mrc_output_len + MRC_DATA_HEADER_SIZE);
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cache = (struct mrc_data_container *)gd->start_addr_sp;
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cache->signature = MRC_DATA_SIGNATURE;
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cache->data_size = gd->arch.mrc_output_len;
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checksum = compute_ip_checksum(gd->arch.mrc_output, cache->data_size);
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debug("Saving %d bytes for MRC output data, checksum %04x\n",
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cache->data_size, checksum);
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cache->checksum = checksum;
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cache->reserved = 0;
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memcpy(cache->data, gd->arch.mrc_output, cache->data_size);
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/* gd->arch.mrc_output now points to the container */
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gd->arch.mrc_output = (char *)cache;
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gd->start_addr_sp &= ~0xf;
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return 0;
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}
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int mrccache_get_region(struct udevice **devp, struct mrc_region *entry)
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{
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const void *blob = gd->fdt_blob;
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int node, mrc_node;
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u32 reg[2];
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int ret;
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/* Find the flash chip within the SPI controller node */
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node = fdtdec_next_compatible(blob, 0, COMPAT_GENERIC_SPI_FLASH);
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if (node < 0) {
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debug("%s: Cannot find SPI flash\n", __func__);
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return -ENOENT;
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}
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if (fdtdec_get_int_array(blob, node, "memory-map", reg, 2))
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return -EINVAL;
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entry->base = reg[0];
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/* Find the place where we put the MRC cache */
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mrc_node = fdt_subnode_offset(blob, node, "rw-mrc-cache");
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if (mrc_node < 0)
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return -EPERM;
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if (fdtdec_get_int_array(blob, mrc_node, "reg", reg, 2))
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return -EINVAL;
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entry->offset = reg[0];
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entry->length = reg[1];
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if (devp) {
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ret = uclass_get_device_by_of_offset(UCLASS_SPI_FLASH, node,
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devp);
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debug("ret = %d\n", ret);
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if (ret)
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return ret;
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}
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return 0;
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}
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int mrccache_save(void)
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{
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struct mrc_data_container *data;
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struct mrc_region entry;
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struct udevice *sf;
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int ret;
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if (!gd->arch.mrc_output_len)
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return 0;
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debug("Saving %d bytes of MRC output data to SPI flash\n",
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gd->arch.mrc_output_len);
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ret = mrccache_get_region(&sf, &entry);
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if (ret)
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goto err_entry;
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data = (struct mrc_data_container *)gd->arch.mrc_output;
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ret = mrccache_update(sf, &entry, data);
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if (!ret) {
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debug("Saved MRC data with checksum %04x\n", data->checksum);
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} else if (ret == -EEXIST) {
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debug("MRC data is the same as last time, skipping save\n");
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ret = 0;
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}
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err_entry:
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if (ret)
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debug("%s: Failed: %d\n", __func__, ret);
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return ret;
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}
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