202 lines
5.5 KiB
C
202 lines
5.5 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* (C) Copyright 2008
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* Marvell Semiconductor <www.marvell.com>
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* Written-by: Prafulla Wadaskar <prafulla@marvell.com>
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*/
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#ifndef _KWBIMAGE_H_
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#define _KWBIMAGE_H_
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#include <compiler.h>
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#include <stdint.h>
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#define KWBIMAGE_MAX_CONFIG ((0x1dc - 0x20)/sizeof(struct reg_config))
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#define MAX_TEMPBUF_LEN 32
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/* NAND ECC Mode */
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#define IBR_HDR_ECC_DEFAULT 0x00
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#define IBR_HDR_ECC_FORCED_HAMMING 0x01
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#define IBR_HDR_ECC_FORCED_RS 0x02
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#define IBR_HDR_ECC_DISABLED 0x03
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/* Boot Type - block ID */
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#define IBR_HDR_I2C_ID 0x4D
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#define IBR_HDR_SPI_ID 0x5A
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#define IBR_HDR_NAND_ID 0x8B
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#define IBR_HDR_SATA_ID 0x78
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#define IBR_HDR_PEX_ID 0x9C
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#define IBR_HDR_UART_ID 0x69
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#define IBR_DEF_ATTRIB 0x00
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#define ALIGN_SUP(x, a) (((x) + (a - 1)) & ~(a - 1))
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/* Structure of the main header, version 0 (Kirkwood, Dove) */
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struct main_hdr_v0 {
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uint8_t blockid; /* 0x0 */
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uint8_t nandeccmode; /* 0x1 */
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uint16_t nandpagesize; /* 0x2-0x3 */
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uint32_t blocksize; /* 0x4-0x7 */
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uint32_t rsvd1; /* 0x8-0xB */
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uint32_t srcaddr; /* 0xC-0xF */
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uint32_t destaddr; /* 0x10-0x13 */
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uint32_t execaddr; /* 0x14-0x17 */
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uint8_t satapiomode; /* 0x18 */
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uint8_t rsvd3; /* 0x19 */
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uint16_t ddrinitdelay; /* 0x1A-0x1B */
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uint16_t rsvd2; /* 0x1C-0x1D */
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uint8_t ext; /* 0x1E */
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uint8_t checksum; /* 0x1F */
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};
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struct ext_hdr_v0_reg {
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uint32_t raddr;
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uint32_t rdata;
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};
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#define EXT_HDR_V0_REG_COUNT ((0x1dc - 0x20) / sizeof(struct ext_hdr_v0_reg))
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struct ext_hdr_v0 {
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uint32_t offset;
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uint8_t reserved[0x20 - sizeof(uint32_t)];
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struct ext_hdr_v0_reg rcfg[EXT_HDR_V0_REG_COUNT];
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uint8_t reserved2[7];
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uint8_t checksum;
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};
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struct kwb_header {
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struct main_hdr_v0 kwb_hdr;
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struct ext_hdr_v0 kwb_exthdr;
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};
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/* Structure of the main header, version 1 (Armada 370/38x/XP) */
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struct main_hdr_v1 {
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uint8_t blockid; /* 0x0 */
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uint8_t flags; /* 0x1 */
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uint16_t reserved2; /* 0x2-0x3 */
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uint32_t blocksize; /* 0x4-0x7 */
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uint8_t version; /* 0x8 */
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uint8_t headersz_msb; /* 0x9 */
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uint16_t headersz_lsb; /* 0xA-0xB */
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uint32_t srcaddr; /* 0xC-0xF */
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uint32_t destaddr; /* 0x10-0x13 */
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uint32_t execaddr; /* 0x14-0x17 */
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uint8_t options; /* 0x18 */
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uint8_t nandblocksize; /* 0x19 */
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uint8_t nandbadblklocation; /* 0x1A */
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uint8_t reserved4; /* 0x1B */
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uint16_t reserved5; /* 0x1C-0x1D */
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uint8_t ext; /* 0x1E */
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uint8_t checksum; /* 0x1F */
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};
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/*
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* Main header options
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*/
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#define MAIN_HDR_V1_OPT_BAUD_DEFAULT 0
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#define MAIN_HDR_V1_OPT_BAUD_2400 0x1
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#define MAIN_HDR_V1_OPT_BAUD_4800 0x2
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#define MAIN_HDR_V1_OPT_BAUD_9600 0x3
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#define MAIN_HDR_V1_OPT_BAUD_19200 0x4
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#define MAIN_HDR_V1_OPT_BAUD_38400 0x5
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#define MAIN_HDR_V1_OPT_BAUD_57600 0x6
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#define MAIN_HDR_V1_OPT_BAUD_115200 0x7
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/*
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* Header for the optional headers, version 1 (Armada 370, Armada XP)
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*/
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struct opt_hdr_v1 {
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uint8_t headertype;
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uint8_t headersz_msb;
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uint16_t headersz_lsb;
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char data[0];
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};
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/*
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* Public Key data in DER format
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*/
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struct pubkey_der_v1 {
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uint8_t key[524];
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};
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/*
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* Signature (RSA 2048)
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*/
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struct sig_v1 {
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uint8_t sig[256];
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};
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/*
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* Structure of secure header (Armada 38x)
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*/
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struct secure_hdr_v1 {
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uint8_t headertype; /* 0x0 */
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uint8_t headersz_msb; /* 0x1 */
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uint16_t headersz_lsb; /* 0x2 - 0x3 */
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uint32_t reserved1; /* 0x4 - 0x7 */
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struct pubkey_der_v1 kak; /* 0x8 - 0x213 */
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uint8_t jtag_delay; /* 0x214 */
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uint8_t reserved2; /* 0x215 */
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uint16_t reserved3; /* 0x216 - 0x217 */
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uint32_t boxid; /* 0x218 - 0x21B */
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uint32_t flashid; /* 0x21C - 0x21F */
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struct sig_v1 hdrsig; /* 0x220 - 0x31F */
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struct sig_v1 imgsig; /* 0x320 - 0x41F */
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struct pubkey_der_v1 csk[16]; /* 0x420 - 0x24DF */
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struct sig_v1 csksig; /* 0x24E0 - 0x25DF */
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uint8_t next; /* 0x25E0 */
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uint8_t reserved4; /* 0x25E1 */
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uint16_t reserved5; /* 0x25E2 - 0x25E3 */
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};
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/*
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* Various values for the opt_hdr_v1->headertype field, describing the
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* different types of optional headers. The "secure" header contains
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* informations related to secure boot (encryption keys, etc.). The
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* "binary" header contains ARM binary code to be executed prior to
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* executing the main payload (usually the bootloader). This is
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* typically used to execute DDR3 training code. The "register" header
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* allows to describe a set of (address, value) tuples that are
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* generally used to configure the DRAM controller.
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*/
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#define OPT_HDR_V1_SECURE_TYPE 0x1
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#define OPT_HDR_V1_BINARY_TYPE 0x2
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#define OPT_HDR_V1_REGISTER_TYPE 0x3
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#define KWBHEADER_V1_SIZE(hdr) \
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(((hdr)->headersz_msb << 16) | le16_to_cpu((hdr)->headersz_lsb))
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enum kwbimage_cmd {
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CMD_INVALID,
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CMD_BOOT_FROM,
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CMD_NAND_ECC_MODE,
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CMD_NAND_PAGE_SIZE,
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CMD_SATA_PIO_MODE,
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CMD_DDR_INIT_DELAY,
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CMD_DATA
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};
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enum kwbimage_cmd_types {
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CFG_INVALID = -1,
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CFG_COMMAND,
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CFG_DATA0,
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CFG_DATA1
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};
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/*
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* functions
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*/
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void init_kwb_image_type (void);
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/*
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* Byte 8 of the image header contains the version number. In the v0
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* header, byte 8 was reserved, and always set to 0. In the v1 header,
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* byte 8 has been changed to a proper field, set to 1.
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*/
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static inline unsigned int image_version(void *header)
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{
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unsigned char *ptr = header;
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return ptr[8];
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}
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#endif /* _KWBIMAGE_H_ */
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