177 lines
4 KiB
C
177 lines
4 KiB
C
#include "bios.h"
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#include "ioport.h"
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#include "pci.h"
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#include <string.h>
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static uint16_t addend;
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static uint8_t bus, bridge_head;
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static bool use_i440fx_routing;
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static int bridge_count;
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uint8_t max_bus;
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static void do_setup_pci_bus(void);
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static void pci_foreach(void(*fn)(uint32_t bdf, uint32_t id, uint8_t type))
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{
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int d, f;
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for (d = 0; d < 32; d++) {
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for (f = 0; f < 8; f++) {
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uint32_t bdf = (bus * 256) + (d * 8) + f;
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uint32_t id = pci_config_readl(bdf, PCI_VENDOR_ID);
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uint16_t vendor;
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uint8_t type;
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/* 0x0000 or 0xFFFF? Skip. */
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vendor = id & 0xFFFF;
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if ((uint16_t)(vendor + 1) <= 1) {
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if (f == 0)
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break;
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else
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continue;
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}
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type = pci_config_readb(bdf, PCI_HEADER_TYPE);
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fn(bdf, id, type);
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if (f == 0 && !(type & PCI_HEADER_TYPE_MULTI_FUNCTION))
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break;
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}
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}
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}
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static void do_setup_pci_irq(uint32_t bdf, int pin)
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{
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int dev = (bdf >> 3) & 0x1f;
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int lnk, irq;
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irq = pci_config_readb(bdf, PCI_INTERRUPT_LINE);
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if (irq != 0)
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return;
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lnk = addend + pin;
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if (use_i440fx_routing)
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lnk += dev - 1;
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else {
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/* Q35 devices 25-31 all use LNKA. Devices 0-24 have
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* a slightly different mapping.
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*/
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if (dev <= 24)
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lnk += dev;
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}
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lnk &= 3;
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irq = lnk & 2 ? 11 : 10;
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pci_config_writeb(bdf, PCI_INTERRUPT_LINE, irq);
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}
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static void do_setup_pci(uint32_t bdf, uint32_t id, uint8_t type)
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{
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uint16_t class;
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uint8_t pin;
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pin = pci_config_readb(bdf, PCI_INTERRUPT_PIN);
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if (pin != 0)
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do_setup_pci_irq(bdf, pin);
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if (type & PCI_HEADER_TYPE_BRIDGE) {
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uint32_t ctl;
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ctl = pci_config_readw(bdf, PCI_BRIDGE_CONTROL);
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pci_config_writew(bdf, PCI_BRIDGE_CONTROL,
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ctl | PCI_BRIDGE_CTL_SERR);
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}
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class = pci_config_readw(bdf, PCI_CLASS_DEVICE);
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switch (class) {
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case PCI_CLASS_STORAGE_IDE:
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pci_config_writel(bdf, 0x10, 0x1f0);
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pci_config_writel(bdf, 0x14, 0x3f4);
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pci_config_writel(bdf, 0x18, 0x170);
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pci_config_writel(bdf, 0x1c, 0x374);
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if (id == (PCI_VENDOR_ID_INTEL | (PCI_DEVICE_ID_INTEL_82371SB_1 << 16))
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|| id == (PCI_VENDOR_ID_INTEL | (PCI_DEVICE_ID_INTEL_82371AB << 16))) {
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/* Enable IDE0 and IDE1. */
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pci_config_writew(bdf, 0x40, 0x8000);
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pci_config_writew(bdf, 0x42, 0x8000);
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}
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break;
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case PCI_CLASS_BRIDGE_PCI:
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pci_config_writeb(bdf, PCI_PRIMARY_BUS, bus);
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/* prevent accidental access to unintended devices */
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pci_config_writeb(bdf, PCI_SUBORDINATE_BUS, 0);
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/*
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* Insert at the head of a linked list of bridges.
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* do_setup_pci_bus will use it later to initialize secondary
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* buses with a recursive call.
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*/
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pci_config_writeb(bdf, PCI_SECONDARY_BUS, bridge_head);
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bridge_head = (uint8_t)(bdf & 0xFF);
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bridge_count++;
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break;
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}
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}
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static void do_setup_pci_bus(void)
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{
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uint8_t save_bus, next_head;
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int i;
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bridge_head = 0xFF;
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bridge_count = 0;
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/* Discover all PCI devices and block bridges */
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pci_foreach(do_setup_pci);
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next_head = bridge_head;
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save_bus = bus;
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/* Configure bridges on this bus and recursively setup new busses */
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for (i = bridge_count; i > 0; i--) {
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uint32_t bdf = (save_bus * 256) + next_head;
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next_head = pci_config_readb(bdf, PCI_SECONDARY_BUS);
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bus = ++max_bus;
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pci_config_writeb(bdf, PCI_SECONDARY_BUS, bus);
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pci_config_writeb(bdf, PCI_SUBORDINATE_BUS, 255);
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/* Add PCI bridge device id for the recursive call. */
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addend += (bdf >> 3) & 0x1f;
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do_setup_pci_bus();
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addend -= (bdf >> 3) & 0x1f;
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pci_config_writeb(bdf, PCI_SUBORDINATE_BUS, max_bus);
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}
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}
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void setup_bios32(void)
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{
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char *bios32 = malloc_fseg_align(16, 16);
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void *bios32_entry_ = &bios32_entry;
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int i;
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memcpy(bios32, "_32_", 4);
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memcpy(bios32 + 4, &bios32_entry_, 4);
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bios32[8] = 0;
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bios32[9] = 1;
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memset(bios32 + 10, 0, 6);
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for (i = 0; i <= 9; i++)
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bios32[10] -= bios32[i];
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}
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void setup_pci(void)
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{
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const int bdf = 0;
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uint32_t id = pci_config_readl(bdf, 0);
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if (id == (PCI_VENDOR_ID_INTEL | (PCI_DEVICE_ID_INTEL_82441 << 16)))
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use_i440fx_routing = true;
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else if (id == (PCI_VENDOR_ID_INTEL | (PCI_DEVICE_ID_INTEL_Q35_MCH << 16)))
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use_i440fx_routing = false;
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else
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panic();
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do_setup_pci_bus();
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setup_bios32();
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}
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