172 lines
6.5 KiB
ReStructuredText
172 lines
6.5 KiB
ReStructuredText
.. _skiboot-5.5.0-rc2:
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skiboot-5.5.0-rc2
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=================
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skiboot-5.5.0-rc2 was released on Monday April 3rd 2017. It is the second
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release candidate of skiboot 5.5, which will become the new stable release
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of skiboot following the 5.4 release, first released November 11th 2016.
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skiboot-5.5.0-rc2 contains all bug fixes as of :ref:`skiboot-5.4.3`
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and :ref:`skiboot-5.1.19` (the currently maintained stable releases).
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For how the skiboot stable releases work, see :ref:`stable-rules` for details.
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The current plan is to cut the final 5.5.0 by April 8th, with skiboot 5.5.0
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being for all POWER8 and POWER9 platforms in op-build v1.16 (Due April 12th).
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This is a short cycle as this release is mainly targetted towards POWER9
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bringup efforts.
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Following skiboot-5.5.0, we will move to a regular six week release cycle,
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similar to op-build, but slightly offset to allow for a short stabilisation
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period. Expected release dates and contents are tracked using GitHub milestone
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and issues: https://github.com/open-power/skiboot/milestones
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Over :ref:`skiboot-5.5.0-rc1`, we have the following changes:
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NVLINK2
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-------
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- Introduce NPU2 support
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NVLink2 is a new feature introduced on POWER9 systems. It is an
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evolution of of the NVLink1 feature included in POWER8+ systems but
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adds several new features including support for GPU address
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translation using the Nest MMU and cache coherence.
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Similar to NVLink1 the functionality is exposed to the OS as a series
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of virtual PCIe devices. However the actual hardware interfaces are
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significantly different which limits the amount of common code that
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can be shared between implementations in the firmware.
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This patch adds basic hardware initialisation and exposure of the
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virtual NVLink2 PCIe devices to the running OS.
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- npu2: Add OPAL calls for nvlink2 address translation services (see :ref:`OPAL_NPU2`)
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Adds three OPAL calls for interacting with NPU2 devices:
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:ref:`OPAL_NPU_INIT_CONTEXT`, :ref:`OPAL_NPU_DESTROY_CONTEXT` and
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:ref:`OPAL_NPU_MAP_LPAR`.
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These are used to setup and configure address translation services
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(ATS) for a process/partition on a given NVLink2 device.
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POWER9
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------
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- hdata/memory: ignore homer and occ reserved ranges
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We populate these from the HOMER BARs in the PBA directly. There's no
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need to take the hostboot supplied values so just ignore the
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corresponding reserved ranges.
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- hdata/vpd: Parse the OpenPOWER OPFR record
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Parse the OpenPOWER FRU VPD (OPFR) record on OpenPOWER instead
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of the VINI records.
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- hdata/vpd: Parse additional VINI records
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These records provide hardware version details, CCIN extension information,
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card type details and hardware characteristics of the FRU
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- hdata/cpu: account for p9 shared caches
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On P9 the L2 and L3 caches are shared between pairs of SMT=4 cores.
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Currently this is not accounted for when creating caches nodes in
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the device tree. This patch adds additional checking so that a
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cache node is only created for the first core in the pair and
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the second core will reference the cache correctly.
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- hdata: print backtraces on HDAT errors
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- hdat: ignore zero length reserves
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Hostboot can export reserved regions with a length of zero and these
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should be ignored rather than being turned into reserved range. While
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we're here fix a memory leak by moving the "too large" region check
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to before we allocate space for the label.
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- SLW: Add init for power9 power management
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This patch adds new function to init core for power9 power management.
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SPECIAL_WKUP_* SCOM registers, if set, can hold the cores from going into
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idle states. Hence, clear PPM_SPECIAL_WKUP_HYP_REG scom register for each
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core during init. (This init are not required for MAMBO)
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PCI
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---
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- hw/phb3: Adjust ECRC on root port dynamically
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The Samsung NVMe adapter is lost when it's connected to PMC 8546 PCIe
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switch, until ECRC is disabled on the root port. We found similar issue
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prevously when Broadcom adapter is connected to same part of PCIe switch
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and it was fixed by commit 60ce59ccd0e9 ("hw/phb3: Disable ECRC on Broadcom
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adapter behind PMC switch"). Unfortunately, the commit doesn't fix
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the Samsung NVMe adapter lost issue.
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This fixes the issues by disable ECRC generation/check on root port
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when PMC 8546 PCIe switch ports are found. This can be extended for
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other PCIe switches or endpoints in future: Each PHB maintains the
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count of PCI devices (PMC 8546 PCIe switch ports currently) which
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require to disable ECRC on root port. The ECRC functionality is
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enabled when first PMC 8546 switch port is probed and disabled when
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last PMC 8546 switch port is destroyed (in PCI hot remove scenario).
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Except PHB's reinitialization after complete reset, the ECRC on
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root port is untouched.
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- core/pci: Fix lost NVMe adapter behind PMC 8546 switch
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The NVMe adapter in below PCI topology is lost. The root cause is
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the presence bit on its PCI slot is missed, but the PCIe link has
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been up. The PCI core doesn't probe the adapter behind the slot,
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leading to lost NVMe adapter in the particular case.
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- PHB3 root port
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- PLX switch 8748 (10b5:8748)
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- PLX swich 9733 (10b5:9733)
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- PMC 8546 swtich (11f8:8546)
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- NVMe adapter (1c58:0023)
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This fixes the issue by overriding the PCI slot presence bit with
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PCIe link state bit.
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- hw/phb4: Locate AER capability position if necessary
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- core/pci: Disable surprise hotplug on root port
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- core/pci: Ignore PCI slot capability on root port
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We are creating PCI slot on root port, where the PCI slot isn't
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supported from hardware. For this case, we shouldn't read the PCI
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slot capability from hardware. When bogus data returned from the
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hardware, we will attempt to the PCI slot's power state or enable
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surprise hotplug functionality. All of them can't be accomplished
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without hardware support.
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This leaves the PCI slot's capability list 0 if PCICAP_EXP_CAP_SLOT
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isn't set in hardware (pcie_cap + 0x2). Otherwise, the PCI slot's
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capability list is retrieved from hardware (pcie_cap + 0x14).
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- phb4: Default to PCIe GEN2 on DD1
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Default to PCIe GEN2 link speeds on DD1 for stability.
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Can be overridden using nvram pcie-max-link-speed=4 parameter.
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- phb3/4: Set max link speed via nvram
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This adds an nvram parameter pcie-max-link-speed to configure the max
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speed of the pcie link. This can be set from the petitboot prompt
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using: ::
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nvram -p ibm,skiboot --update-config pcie-max-link-speed=4
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This takes preference over anything set in the device tree and is
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global to all PHBs.
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Tests
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-----
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- Mambo/Qemu boot tests: expect (and fail) on checkstop
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This allows us to fail a lot faster if we checkstop
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