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armemu: Implement UXTAB16
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parent
0fd731ee63
commit
1c7f77334c
1 changed files with 25 additions and 10 deletions
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@ -6101,17 +6101,32 @@ L_stm_s_takeabort:
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return 1;
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}
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case 0x6c:
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if ((instr & 0xf03f0) == 0xf0070) { //uxtb16
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u8 rm_idx = BITS(0, 3);
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u8 rd_idx = BITS(12, 15);
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u32 rm_val = state->Reg[rm_idx];
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u32 rotation = BITS(10, 11) * 8;
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u32 in = ((rm_val << (32 - rotation)) | (rm_val >> rotation));
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state->Reg[rd_idx] = in & 0x00FF00FF;
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case 0x6c: // UXTB16 and UXTAB16
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{
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const u8 rm_idx = BITS(0, 3);
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const u8 rn_idx = BITS(16, 19);
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const u8 rd_idx = BITS(12, 15);
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const u32 rm_val = state->Reg[rm_idx];
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const u32 rn_val = state->Reg[rn_idx];
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const u32 rotation = BITS(10, 11) * 8;
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const u32 rotated_rm = ((rm_val << (32 - rotation)) | (rm_val >> rotation));
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// UXTB16
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if ((instr & 0xf03f0) == 0xf0070) {
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state->Reg[rd_idx] = rotated_rm & 0x00FF00FF;
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}
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else { // UXTAB16
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const u8 lo_rotated = (rotated_rm & 0xFF);
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const u16 lo_result = (rn_val & 0xFFFF) + (u16)lo_rotated;
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const u8 hi_rotated = (rotated_rm >> 16) & 0xFF;
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const u16 hi_result = (rn_val >> 16) + (u16)hi_rotated;
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state->Reg[rd_idx] = ((hi_result << 16) | (lo_result & 0xFFFF));
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}
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return 1;
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} else
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printf ("Unhandled v6 insn: uxtab16\n");
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}
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break;
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case 0x6e: {
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ARMword Rm;
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