mirror of
https://github.com/Lime3DS/Lime3DS
synced 2024-12-27 01:22:37 -06:00
core: Make the ARM disassembler use std::string internally
This commit is contained in:
Lioncash
parent
5d95d038a0
commit
403c84cdab
5 changed files with 147 additions and 195 deletions
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@ -37,7 +37,7 @@ void CallstackWidget::OnCPUStepped()
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/* TODO (mattvail) clean me, move to debugger interface */
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u32 insn = Memory::Read32(call_addr);
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if (disasm->decode(insn) == OP_BL)
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if (disasm->Decode(insn) == OP_BL)
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{
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std::string name;
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// ripped from disasm
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@ -36,22 +36,20 @@ QVariant DisassemblerModel::data(const QModelIndex& index, int role) const {
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switch (role) {
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case Qt::DisplayRole:
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{
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static char result[255];
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u32 address = base_address + index.row() * 4;
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u32 instr = Memory::Read32(address);
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ARM_Disasm::disasm(address, instr, result);
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std::string disassembly = ARM_Disasm::Disassemble(address, instr);
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if (index.column() == 0) {
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return QString("0x%1").arg((uint)(address), 8, 16, QLatin1Char('0'));
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} else if (index.column() == 1) {
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return QString::fromLatin1(result);
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return QString::fromStdString(disassembly);
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} else if (index.column() == 2) {
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if(Symbols::HasSymbol(address)) {
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TSymbol symbol = Symbols::GetSymbol(address);
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return QString("%1 - Size:%2").arg(QString::fromStdString(symbol.name))
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.arg(symbol.size / 4); // divide by 4 to get instruction count
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} else if (ARM_Disasm::decode(instr) == OP_BL) {
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} else if (ARM_Disasm::Decode(instr) == OP_BL) {
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u32 offset = instr & 0xFFFFFF;
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// Sign-extend the 24-bit offset
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@ -1,8 +1,8 @@
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// Copyright 2006 The Android Open Source Project
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#include <stdio.h>
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#include <string.h>
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#include <string>
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#include "common/string_util.h"
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#include "core/arm/disassembler/arm_disasm.h"
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static const char *cond_names[] = {
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@ -135,20 +135,14 @@ static const char* cond_to_str(int cond) {
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return cond_names[cond];
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}
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char *ARM_Disasm::disasm(uint32_t addr, uint32_t insn, char *result)
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std::string ARM_Disasm::Disassemble(uint32_t addr, uint32_t insn)
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{
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static char buf[80];
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char *ptr;
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ptr = result ? result : buf;
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Opcode opcode = decode(insn);
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Opcode opcode = Decode(insn);
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switch (opcode) {
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case OP_INVALID:
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sprintf(ptr, "Invalid");
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return ptr;
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return "Invalid";
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case OP_UNDEFINED:
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sprintf(ptr, "Undefined");
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return ptr;
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return "Undefined";
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case OP_ADC:
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case OP_ADD:
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case OP_AND:
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@ -165,28 +159,26 @@ char *ARM_Disasm::disasm(uint32_t addr, uint32_t insn, char *result)
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case OP_SUB:
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case OP_TEQ:
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case OP_TST:
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return disasm_alu(opcode, insn, ptr);
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return DisassembleALU(opcode, insn);
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case OP_B:
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case OP_BL:
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return disasm_branch(addr, opcode, insn, ptr);
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return DisassembleBranch(addr, opcode, insn);
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case OP_BKPT:
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return disasm_bkpt(insn, ptr);
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return DisassembleBKPT(insn);
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case OP_BLX:
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// not supported yet
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break;
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case OP_BX:
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return disasm_bx(insn, ptr);
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return DisassembleBX(insn);
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case OP_CDP:
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sprintf(ptr, "cdp");
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return ptr;
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return "cdp";
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case OP_CLZ:
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return disasm_clz(insn, ptr);
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return DisassembleCLZ(insn);
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case OP_LDC:
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sprintf(ptr, "ldc");
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return ptr;
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return "ldc";
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case OP_LDM:
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case OP_STM:
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return disasm_memblock(opcode, insn, ptr);
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return DisassembleMemblock(opcode, insn);
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case OP_LDR:
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case OP_LDRB:
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case OP_LDRBT:
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@ -195,53 +187,52 @@ char *ARM_Disasm::disasm(uint32_t addr, uint32_t insn, char *result)
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case OP_STRB:
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case OP_STRBT:
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case OP_STRT:
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return disasm_mem(insn, ptr);
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return DisassembleMem(insn);
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case OP_LDRH:
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case OP_LDRSB:
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case OP_LDRSH:
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case OP_STRH:
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return disasm_memhalf(insn, ptr);
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return DisassembleMemHalf(insn);
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case OP_MCR:
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case OP_MRC:
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return disasm_mcr(opcode, insn, ptr);
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return DisassembleMCR(opcode, insn);
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case OP_MLA:
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return disasm_mla(opcode, insn, ptr);
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return DisassembleMLA(opcode, insn);
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case OP_MRS:
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return disasm_mrs(insn, ptr);
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return DisassembleMRS(insn);
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case OP_MSR:
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return disasm_msr(insn, ptr);
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return DisassembleMSR(insn);
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case OP_MUL:
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return disasm_mul(opcode, insn, ptr);
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return DisassembleMUL(opcode, insn);
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case OP_PLD:
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return disasm_pld(insn, ptr);
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return DisassemblePLD(insn);
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case OP_STC:
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sprintf(ptr, "stc");
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return ptr;
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return "stc";
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case OP_SWI:
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return disasm_swi(insn, ptr);
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return DisassembleSWI(insn);
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case OP_SWP:
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case OP_SWPB:
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return disasm_swp(opcode, insn, ptr);
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return DisassembleSWP(opcode, insn);
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case OP_UMLAL:
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case OP_UMULL:
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case OP_SMLAL:
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case OP_SMULL:
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return disasm_umlal(opcode, insn, ptr);
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return DisassembleUMLAL(opcode, insn);
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default:
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sprintf(ptr, "Error");
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return ptr;
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return "Error";
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}
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return NULL;
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}
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char *ARM_Disasm::disasm_alu(Opcode opcode, uint32_t insn, char *ptr)
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std::string ARM_Disasm::DisassembleALU(Opcode opcode, uint32_t insn)
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{
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static const uint8_t kNoOperand1 = 1;
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static const uint8_t kNoDest = 2;
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static const uint8_t kNoSbit = 4;
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char rn_str[20];
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char rd_str[20];
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std::string rn_str;
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std::string rd_str;
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uint8_t flags = 0;
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uint8_t cond = (insn >> 28) & 0xf;
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uint8_t is_immed = (insn >> 25) & 0x1;
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@ -269,14 +260,14 @@ char *ARM_Disasm::disasm_alu(Opcode opcode, uint32_t insn, char *ptr)
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// The "mov" instruction ignores the first operand (rn).
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rn_str[0] = 0;
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if ((flags & kNoOperand1) == 0) {
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sprintf(rn_str, "r%d, ", rn);
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rn_str = StringFromFormat("r%d, ", rn);
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}
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// The following instructions do not write the result register (rd):
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// tst, teq, cmp, cmn.
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rd_str[0] = 0;
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if ((flags & kNoDest) == 0) {
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sprintf(rd_str, "r%d, ", rd);
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rd_str = StringFromFormat("r%d, ", rd);
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}
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const char *sbit_str = "";
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@ -284,9 +275,8 @@ char *ARM_Disasm::disasm_alu(Opcode opcode, uint32_t insn, char *ptr)
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sbit_str = "s";
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if (is_immed) {
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sprintf(ptr, "%s%s%s\t%s%s#%u ; 0x%x",
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opname, cond_to_str(cond), sbit_str, rd_str, rn_str, immed, immed);
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return ptr;
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return StringFromFormat("%s%s%s\t%s%s#%u ; 0x%x",
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opname, cond_to_str(cond), sbit_str, rd_str.c_str(), rn_str.c_str(), immed, immed);
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}
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uint8_t shift_is_reg = (insn >> 4) & 1;
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@ -300,33 +290,29 @@ char *ARM_Disasm::disasm_alu(Opcode opcode, uint32_t insn, char *ptr)
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rotated_val = (rotated_val >> rotate2) | (rotated_val << (32 - rotate2));
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if (!shift_is_reg && shift_type == 0 && shift_amount == 0) {
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sprintf(ptr, "%s%s%s\t%s%sr%d",
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opname, cond_to_str(cond), sbit_str, rd_str, rn_str, rm);
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return ptr;
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return StringFromFormat("%s%s%s\t%s%sr%d",
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opname, cond_to_str(cond), sbit_str, rd_str.c_str(), rn_str.c_str(), rm);
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}
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const char *shift_name = shift_names[shift_type];
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if (shift_is_reg) {
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sprintf(ptr, "%s%s%s\t%s%sr%d, %s r%d",
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opname, cond_to_str(cond), sbit_str, rd_str, rn_str, rm,
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return StringFromFormat("%s%s%s\t%s%sr%d, %s r%d",
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opname, cond_to_str(cond), sbit_str, rd_str.c_str(), rn_str.c_str(), rm,
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shift_name, rs);
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return ptr;
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}
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if (shift_amount == 0) {
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if (shift_type == 3) {
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sprintf(ptr, "%s%s%s\t%s%sr%d, RRX",
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opname, cond_to_str(cond), sbit_str, rd_str, rn_str, rm);
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return ptr;
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return StringFromFormat("%s%s%s\t%s%sr%d, RRX",
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opname, cond_to_str(cond), sbit_str, rd_str.c_str(), rn_str.c_str(), rm);
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}
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shift_amount = 32;
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}
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sprintf(ptr, "%s%s%s\t%s%sr%d, %s #%u",
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opname, cond_to_str(cond), sbit_str, rd_str, rn_str, rm,
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return StringFromFormat("%s%s%s\t%s%sr%d, %s #%u",
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opname, cond_to_str(cond), sbit_str, rd_str.c_str(), rn_str.c_str(), rm,
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shift_name, shift_amount);
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return ptr;
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}
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char *ARM_Disasm::disasm_branch(uint32_t addr, Opcode opcode, uint32_t insn, char *ptr)
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std::string ARM_Disasm::DisassembleBranch(uint32_t addr, Opcode opcode, uint32_t insn)
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{
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uint8_t cond = (insn >> 28) & 0xf;
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uint32_t offset = insn & 0xffffff;
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@ -339,37 +325,34 @@ char *ARM_Disasm::disasm_branch(uint32_t addr, Opcode opcode, uint32_t insn, cha
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offset += 8;
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addr += offset;
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const char *opname = opcode_names[opcode];
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sprintf(ptr, "%s%s\t0x%x", opname, cond_to_str(cond), addr);
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return ptr;
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return StringFromFormat("%s%s\t0x%x", opname, cond_to_str(cond), addr);
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}
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char *ARM_Disasm::disasm_bx(uint32_t insn, char *ptr)
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std::string ARM_Disasm::DisassembleBX(uint32_t insn)
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{
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uint8_t cond = (insn >> 28) & 0xf;
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uint8_t rn = insn & 0xf;
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sprintf(ptr, "bx%s\tr%d", cond_to_str(cond), rn);
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return ptr;
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return StringFromFormat("bx%s\tr%d", cond_to_str(cond), rn);
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}
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char *ARM_Disasm::disasm_bkpt(uint32_t insn, char *ptr)
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std::string ARM_Disasm::DisassembleBKPT(uint32_t insn)
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{
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uint32_t immed = (((insn >> 8) & 0xfff) << 4) | (insn & 0xf);
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sprintf(ptr, "bkpt\t#%d", immed);
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return ptr;
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return StringFromFormat("bkpt\t#%d", immed);
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}
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char *ARM_Disasm::disasm_clz(uint32_t insn, char *ptr)
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std::string ARM_Disasm::DisassembleCLZ(uint32_t insn)
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{
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uint8_t cond = (insn >> 28) & 0xf;
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uint8_t rd = (insn >> 12) & 0xf;
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uint8_t rm = insn & 0xf;
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sprintf(ptr, "clz%s\tr%d, r%d", cond_to_str(cond), rd, rm);
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return ptr;
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return StringFromFormat("clz%s\tr%d, r%d", cond_to_str(cond), rd, rm);
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}
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char *ARM_Disasm::disasm_memblock(Opcode opcode, uint32_t insn, char *ptr)
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std::string ARM_Disasm::DisassembleMemblock(Opcode opcode, uint32_t insn)
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{
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char tmp_reg[10], tmp_list[80];
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std::string tmp_reg;
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std::string tmp_list;
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uint8_t cond = (insn >> 28) & 0xf;
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uint8_t write_back = (insn >> 21) & 0x1;
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@ -393,8 +376,7 @@ char *ARM_Disasm::disasm_memblock(Opcode opcode, uint32_t insn, char *ptr)
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tmp_list[0] = 0;
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for (int ii = 0; ii < 16; ++ii) {
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if (reg_list & (1 << ii)) {
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sprintf(tmp_reg, "%sr%d", comma, ii);
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strcat(tmp_list, tmp_reg);
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tmp_list += StringFromFormat("%sr%d", comma, ii);
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comma = ",";
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}
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}
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@ -414,12 +396,11 @@ char *ARM_Disasm::disasm_memblock(Opcode opcode, uint32_t insn, char *ptr)
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}
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}
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sprintf(ptr, "%s%s%s\tr%d%s, {%s}%s",
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opname, cond_to_str(cond), addr_mode, rn, bang, tmp_list, carret);
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return ptr;
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return StringFromFormat("%s%s%s\tr%d%s, {%s}%s",
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opname, cond_to_str(cond), addr_mode, rn, bang, tmp_list.c_str(), carret);
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}
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char *ARM_Disasm::disasm_mem(uint32_t insn, char *ptr)
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std::string ARM_Disasm::DisassembleMem(uint32_t insn)
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{
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uint8_t cond = (insn >> 28) & 0xf;
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uint8_t is_reg = (insn >> 25) & 0x1;
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@ -451,20 +432,20 @@ char *ARM_Disasm::disasm_mem(uint32_t insn, char *ptr)
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if (is_reg == 0) {
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if (is_pre) {
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if (offset == 0) {
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sprintf(ptr, "%s%s%s\tr%d, [r%d]",
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return StringFromFormat("%s%s%s\tr%d, [r%d]",
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opname, cond_to_str(cond), byte, rd, rn);
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} else {
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sprintf(ptr, "%s%s%s\tr%d, [r%d, #%s%u]%s",
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return StringFromFormat("%s%s%s\tr%d, [r%d, #%s%u]%s",
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opname, cond_to_str(cond), byte, rd, rn, minus, offset, bang);
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}
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} else {
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const char *transfer = "";
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if (write_back)
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transfer = "t";
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sprintf(ptr, "%s%s%s%s\tr%d, [r%d], #%s%u",
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return StringFromFormat("%s%s%s%s\tr%d, [r%d], #%s%u",
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opname, cond_to_str(cond), byte, transfer, rd, rn, minus, offset);
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}
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return ptr;
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}
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uint8_t rm = insn & 0xf;
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@ -476,21 +457,18 @@ char *ARM_Disasm::disasm_mem(uint32_t insn, char *ptr)
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if (is_pre) {
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if (shift_amount == 0) {
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if (shift_type == 0) {
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sprintf(ptr, "%s%s%s\tr%d, [r%d, %sr%d]%s",
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return StringFromFormat("%s%s%s\tr%d, [r%d, %sr%d]%s",
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opname, cond_to_str(cond), byte, rd, rn, minus, rm, bang);
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return ptr;
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}
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if (shift_type == 3) {
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sprintf(ptr, "%s%s%s\tr%d, [r%d, %sr%d, RRX]%s",
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return StringFromFormat("%s%s%s\tr%d, [r%d, %sr%d, RRX]%s",
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opname, cond_to_str(cond), byte, rd, rn, minus, rm, bang);
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return ptr;
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}
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shift_amount = 32;
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}
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sprintf(ptr, "%s%s%s\tr%d, [r%d, %sr%d, %s #%u]%s",
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return StringFromFormat("%s%s%s\tr%d, [r%d, %sr%d, %s #%u]%s",
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opname, cond_to_str(cond), byte, rd, rn, minus, rm,
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shift_name, shift_amount, bang);
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return ptr;
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}
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const char *transfer = "";
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@ -499,25 +477,22 @@ char *ARM_Disasm::disasm_mem(uint32_t insn, char *ptr)
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if (shift_amount == 0) {
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if (shift_type == 0) {
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sprintf(ptr, "%s%s%s%s\tr%d, [r%d], %sr%d",
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return StringFromFormat("%s%s%s%s\tr%d, [r%d], %sr%d",
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opname, cond_to_str(cond), byte, transfer, rd, rn, minus, rm);
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return ptr;
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}
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if (shift_type == 3) {
|
||||
sprintf(ptr, "%s%s%s%s\tr%d, [r%d], %sr%d, RRX",
|
||||
return StringFromFormat("%s%s%s%s\tr%d, [r%d], %sr%d, RRX",
|
||||
opname, cond_to_str(cond), byte, transfer, rd, rn, minus, rm);
|
||||
return ptr;
|
||||
}
|
||||
shift_amount = 32;
|
||||
}
|
||||
|
||||
sprintf(ptr, "%s%s%s%s\tr%d, [r%d], %sr%d, %s #%u",
|
||||
return StringFromFormat("%s%s%s%s\tr%d, [r%d], %sr%d, %s #%u",
|
||||
opname, cond_to_str(cond), byte, transfer, rd, rn, minus, rm,
|
||||
shift_name, shift_amount);
|
||||
return ptr;
|
||||
}
|
||||
|
||||
char *ARM_Disasm::disasm_memhalf(uint32_t insn, char *ptr)
|
||||
std::string ARM_Disasm::DisassembleMemHalf(uint32_t insn)
|
||||
{
|
||||
uint8_t cond = (insn >> 28) & 0xf;
|
||||
uint8_t is_load = (insn >> 20) & 0x1;
|
||||
|
|
@ -553,29 +528,27 @@ char *ARM_Disasm::disasm_memhalf(uint32_t insn, char *ptr)
|
|||
if (is_immed) {
|
||||
if (is_pre) {
|
||||
if (offset == 0) {
|
||||
sprintf(ptr, "%s%sh\tr%d, [r%d]", opname, cond_to_str(cond), rd, rn);
|
||||
return StringFromFormat("%s%sh\tr%d, [r%d]", opname, cond_to_str(cond), rd, rn);
|
||||
} else {
|
||||
sprintf(ptr, "%s%sh\tr%d, [r%d, #%s%u]%s",
|
||||
return StringFromFormat("%s%sh\tr%d, [r%d, #%s%u]%s",
|
||||
opname, cond_to_str(cond), rd, rn, minus, offset, bang);
|
||||
}
|
||||
} else {
|
||||
sprintf(ptr, "%s%sh\tr%d, [r%d], #%s%u",
|
||||
return StringFromFormat("%s%sh\tr%d, [r%d], #%s%u",
|
||||
opname, cond_to_str(cond), rd, rn, minus, offset);
|
||||
}
|
||||
return ptr;
|
||||
}
|
||||
|
||||
if (is_pre) {
|
||||
sprintf(ptr, "%s%sh\tr%d, [r%d, %sr%d]%s",
|
||||
return StringFromFormat("%s%sh\tr%d, [r%d, %sr%d]%s",
|
||||
opname, cond_to_str(cond), rd, rn, minus, rm, bang);
|
||||
} else {
|
||||
sprintf(ptr, "%s%sh\tr%d, [r%d], %sr%d",
|
||||
return StringFromFormat("%s%sh\tr%d, [r%d], %sr%d",
|
||||
opname, cond_to_str(cond), rd, rn, minus, rm);
|
||||
}
|
||||
return ptr;
|
||||
}
|
||||
|
||||
char *ARM_Disasm::disasm_mcr(Opcode opcode, uint32_t insn, char *ptr)
|
||||
std::string ARM_Disasm::DisassembleMCR(Opcode opcode, uint32_t insn)
|
||||
{
|
||||
uint8_t cond = (insn >> 28) & 0xf;
|
||||
uint8_t crn = (insn >> 16) & 0xf;
|
||||
|
|
@ -585,12 +558,11 @@ char *ARM_Disasm::disasm_mcr(Opcode opcode, uint32_t insn, char *ptr)
|
|||
uint8_t crm = insn & 0xf;
|
||||
|
||||
const char *opname = opcode_names[opcode];
|
||||
sprintf(ptr, "%s%s\t%d, 0, r%d, cr%d, cr%d, {%d}",
|
||||
return StringFromFormat("%s%s\t%d, 0, r%d, cr%d, cr%d, {%d}",
|
||||
opname, cond_to_str(cond), cpnum, crd, crn, crm, opcode2);
|
||||
return ptr;
|
||||
}
|
||||
|
||||
char *ARM_Disasm::disasm_mla(Opcode opcode, uint32_t insn, char *ptr)
|
||||
std::string ARM_Disasm::DisassembleMLA(Opcode opcode, uint32_t insn)
|
||||
{
|
||||
uint8_t cond = (insn >> 28) & 0xf;
|
||||
uint8_t rd = (insn >> 16) & 0xf;
|
||||
|
|
@ -600,12 +572,11 @@ char *ARM_Disasm::disasm_mla(Opcode opcode, uint32_t insn, char *ptr)
|
|||
uint8_t bit_s = (insn >> 20) & 1;
|
||||
|
||||
const char *opname = opcode_names[opcode];
|
||||
sprintf(ptr, "%s%s%s\tr%d, r%d, r%d, r%d",
|
||||
return StringFromFormat("%s%s%s\tr%d, r%d, r%d, r%d",
|
||||
opname, cond_to_str(cond), bit_s ? "s" : "", rd, rm, rs, rn);
|
||||
return ptr;
|
||||
}
|
||||
|
||||
char *ARM_Disasm::disasm_umlal(Opcode opcode, uint32_t insn, char *ptr)
|
||||
std::string ARM_Disasm::DisassembleUMLAL(Opcode opcode, uint32_t insn)
|
||||
{
|
||||
uint8_t cond = (insn >> 28) & 0xf;
|
||||
uint8_t rdhi = (insn >> 16) & 0xf;
|
||||
|
|
@ -615,12 +586,11 @@ char *ARM_Disasm::disasm_umlal(Opcode opcode, uint32_t insn, char *ptr)
|
|||
uint8_t bit_s = (insn >> 20) & 1;
|
||||
|
||||
const char *opname = opcode_names[opcode];
|
||||
sprintf(ptr, "%s%s%s\tr%d, r%d, r%d, r%d",
|
||||
return StringFromFormat("%s%s%s\tr%d, r%d, r%d, r%d",
|
||||
opname, cond_to_str(cond), bit_s ? "s" : "", rdlo, rdhi, rm, rs);
|
||||
return ptr;
|
||||
}
|
||||
|
||||
char *ARM_Disasm::disasm_mul(Opcode opcode, uint32_t insn, char *ptr)
|
||||
std::string ARM_Disasm::DisassembleMUL(Opcode opcode, uint32_t insn)
|
||||
{
|
||||
uint8_t cond = (insn >> 28) & 0xf;
|
||||
uint8_t rd = (insn >> 16) & 0xf;
|
||||
|
|
@ -629,22 +599,20 @@ char *ARM_Disasm::disasm_mul(Opcode opcode, uint32_t insn, char *ptr)
|
|||
uint8_t bit_s = (insn >> 20) & 1;
|
||||
|
||||
const char *opname = opcode_names[opcode];
|
||||
sprintf(ptr, "%s%s%s\tr%d, r%d, r%d",
|
||||
return StringFromFormat("%s%s%s\tr%d, r%d, r%d",
|
||||
opname, cond_to_str(cond), bit_s ? "s" : "", rd, rm, rs);
|
||||
return ptr;
|
||||
}
|
||||
|
||||
char *ARM_Disasm::disasm_mrs(uint32_t insn, char *ptr)
|
||||
std::string ARM_Disasm::DisassembleMRS(uint32_t insn)
|
||||
{
|
||||
uint8_t cond = (insn >> 28) & 0xf;
|
||||
uint8_t rd = (insn >> 12) & 0xf;
|
||||
uint8_t ps = (insn >> 22) & 1;
|
||||
|
||||
sprintf(ptr, "mrs%s\tr%d, %s", cond_to_str(cond), rd, ps ? "spsr" : "cpsr");
|
||||
return ptr;
|
||||
return StringFromFormat("mrs%s\tr%d, %s", cond_to_str(cond), rd, ps ? "spsr" : "cpsr");
|
||||
}
|
||||
|
||||
char *ARM_Disasm::disasm_msr(uint32_t insn, char *ptr)
|
||||
std::string ARM_Disasm::DisassembleMSR(uint32_t insn)
|
||||
{
|
||||
char flags[8];
|
||||
int flag_index = 0;
|
||||
|
|
@ -668,19 +636,17 @@ char *ARM_Disasm::disasm_msr(uint32_t insn, char *ptr)
|
|||
uint8_t rotate = (insn >> 8) & 0xf;
|
||||
uint8_t rotate2 = rotate << 1;
|
||||
uint32_t rotated_val = (immed >> rotate2) | (immed << (32 - rotate2));
|
||||
sprintf(ptr, "msr%s\t%s_%s, #0x%x",
|
||||
return StringFromFormat("msr%s\t%s_%s, #0x%x",
|
||||
cond_to_str(cond), pd ? "spsr" : "cpsr", flags, rotated_val);
|
||||
return ptr;
|
||||
}
|
||||
|
||||
uint8_t rm = insn & 0xf;
|
||||
|
||||
sprintf(ptr, "msr%s\t%s_%s, r%d",
|
||||
return StringFromFormat("msr%s\t%s_%s, r%d",
|
||||
cond_to_str(cond), pd ? "spsr" : "cpsr", flags, rm);
|
||||
return ptr;
|
||||
}
|
||||
|
||||
char *ARM_Disasm::disasm_pld(uint32_t insn, char *ptr)
|
||||
std::string ARM_Disasm::DisassemblePLD(uint32_t insn)
|
||||
{
|
||||
uint8_t is_reg = (insn >> 25) & 0x1;
|
||||
uint8_t is_up = (insn >> 23) & 0x1;
|
||||
|
|
@ -692,29 +658,26 @@ char *ARM_Disasm::disasm_pld(uint32_t insn, char *ptr)
|
|||
|
||||
if (is_reg) {
|
||||
uint8_t rm = insn & 0xf;
|
||||
sprintf(ptr, "pld\t[r%d, %sr%d]", rn, minus, rm);
|
||||
return ptr;
|
||||
return StringFromFormat("pld\t[r%d, %sr%d]", rn, minus, rm);
|
||||
}
|
||||
|
||||
uint16_t offset = insn & 0xfff;
|
||||
if (offset == 0) {
|
||||
sprintf(ptr, "pld\t[r%d]", rn);
|
||||
return StringFromFormat("pld\t[r%d]", rn);
|
||||
} else {
|
||||
sprintf(ptr, "pld\t[r%d, #%s%u]", rn, minus, offset);
|
||||
return StringFromFormat("pld\t[r%d, #%s%u]", rn, minus, offset);
|
||||
}
|
||||
return ptr;
|
||||
}
|
||||
|
||||
char *ARM_Disasm::disasm_swi(uint32_t insn, char *ptr)
|
||||
std::string ARM_Disasm::DisassembleSWI(uint32_t insn)
|
||||
{
|
||||
uint8_t cond = (insn >> 28) & 0xf;
|
||||
uint32_t sysnum = insn & 0x00ffffff;
|
||||
|
||||
sprintf(ptr, "swi%s 0x%x", cond_to_str(cond), sysnum);
|
||||
return ptr;
|
||||
return StringFromFormat("swi%s 0x%x", cond_to_str(cond), sysnum);
|
||||
}
|
||||
|
||||
char *ARM_Disasm::disasm_swp(Opcode opcode, uint32_t insn, char *ptr)
|
||||
std::string ARM_Disasm::DisassembleSWP(Opcode opcode, uint32_t insn)
|
||||
{
|
||||
uint8_t cond = (insn >> 28) & 0xf;
|
||||
uint8_t rn = (insn >> 16) & 0xf;
|
||||
|
|
@ -722,26 +685,25 @@ char *ARM_Disasm::disasm_swp(Opcode opcode, uint32_t insn, char *ptr)
|
|||
uint8_t rm = insn & 0xf;
|
||||
|
||||
const char *opname = opcode_names[opcode];
|
||||
sprintf(ptr, "%s%s\tr%d, r%d, [r%d]", opname, cond_to_str(cond), rd, rm, rn);
|
||||
return ptr;
|
||||
return StringFromFormat("%s%s\tr%d, r%d, [r%d]", opname, cond_to_str(cond), rd, rm, rn);
|
||||
}
|
||||
|
||||
Opcode ARM_Disasm::decode(uint32_t insn) {
|
||||
Opcode ARM_Disasm::Decode(uint32_t insn) {
|
||||
uint32_t bits27_26 = (insn >> 26) & 0x3;
|
||||
switch (bits27_26) {
|
||||
case 0x0:
|
||||
return decode00(insn);
|
||||
return Decode00(insn);
|
||||
case 0x1:
|
||||
return decode01(insn);
|
||||
return Decode01(insn);
|
||||
case 0x2:
|
||||
return decode10(insn);
|
||||
return Decode10(insn);
|
||||
case 0x3:
|
||||
return decode11(insn);
|
||||
return Decode11(insn);
|
||||
}
|
||||
return OP_INVALID;
|
||||
}
|
||||
|
||||
Opcode ARM_Disasm::decode00(uint32_t insn) {
|
||||
Opcode ARM_Disasm::Decode00(uint32_t insn) {
|
||||
uint8_t bit25 = (insn >> 25) & 0x1;
|
||||
uint8_t bit4 = (insn >> 4) & 0x1;
|
||||
if (bit25 == 0 && bit4 == 1) {
|
||||
|
|
@ -767,21 +729,21 @@ Opcode ARM_Disasm::decode00(uint32_t insn) {
|
|||
return OP_SWP;
|
||||
}
|
||||
// One of the multiply instructions
|
||||
return decode_mul(insn);
|
||||
return DecodeMUL(insn);
|
||||
}
|
||||
|
||||
uint8_t bit7 = (insn >> 7) & 0x1;
|
||||
if (bit7 == 1) {
|
||||
// One of the load/store halfword/byte instructions
|
||||
return decode_ldrh(insn);
|
||||
return DecodeLDRH(insn);
|
||||
}
|
||||
}
|
||||
|
||||
// One of the data processing instructions
|
||||
return decode_alu(insn);
|
||||
return DecodeALU(insn);
|
||||
}
|
||||
|
||||
Opcode ARM_Disasm::decode01(uint32_t insn) {
|
||||
Opcode ARM_Disasm::Decode01(uint32_t insn) {
|
||||
uint8_t is_reg = (insn >> 25) & 0x1;
|
||||
uint8_t bit4 = (insn >> 4) & 0x1;
|
||||
if (is_reg == 1 && bit4 == 1)
|
||||
|
|
@ -808,7 +770,7 @@ Opcode ARM_Disasm::decode01(uint32_t insn) {
|
|||
return OP_STR;
|
||||
}
|
||||
|
||||
Opcode ARM_Disasm::decode10(uint32_t insn) {
|
||||
Opcode ARM_Disasm::Decode10(uint32_t insn) {
|
||||
uint8_t bit25 = (insn >> 25) & 0x1;
|
||||
if (bit25 == 0) {
|
||||
// LDM/STM
|
||||
|
|
@ -833,7 +795,7 @@ Opcode ARM_Disasm::decode10(uint32_t insn) {
|
|||
return OP_BL;
|
||||
}
|
||||
|
||||
Opcode ARM_Disasm::decode11(uint32_t insn) {
|
||||
Opcode ARM_Disasm::Decode11(uint32_t insn) {
|
||||
uint8_t bit25 = (insn >> 25) & 0x1;
|
||||
if (bit25 == 0) {
|
||||
// LDC, SDC
|
||||
|
|
@ -882,7 +844,7 @@ Opcode ARM_Disasm::decode11(uint32_t insn) {
|
|||
return OP_MCR;
|
||||
}
|
||||
|
||||
Opcode ARM_Disasm::decode_mul(uint32_t insn) {
|
||||
Opcode ARM_Disasm::DecodeMUL(uint32_t insn) {
|
||||
uint8_t bit24 = (insn >> 24) & 0x1;
|
||||
if (bit24 != 0) {
|
||||
// This is an unexpected bit pattern. Create an undefined
|
||||
|
|
@ -916,7 +878,7 @@ Opcode ARM_Disasm::decode_mul(uint32_t insn) {
|
|||
return OP_SMLAL;
|
||||
}
|
||||
|
||||
Opcode ARM_Disasm::decode_ldrh(uint32_t insn) {
|
||||
Opcode ARM_Disasm::DecodeLDRH(uint32_t insn) {
|
||||
uint8_t is_load = (insn >> 20) & 0x1;
|
||||
uint8_t bits_65 = (insn >> 5) & 0x3;
|
||||
if (is_load) {
|
||||
|
|
@ -946,7 +908,7 @@ Opcode ARM_Disasm::decode_ldrh(uint32_t insn) {
|
|||
return OP_STRH;
|
||||
}
|
||||
|
||||
Opcode ARM_Disasm::decode_alu(uint32_t insn) {
|
||||
Opcode ARM_Disasm::DecodeALU(uint32_t insn) {
|
||||
uint8_t is_immed = (insn >> 25) & 0x1;
|
||||
uint8_t opcode = (insn >> 21) & 0xf;
|
||||
uint8_t bit_s = (insn >> 20) & 1;
|
||||
|
|
|
|||
|
|
@ -1,9 +1,9 @@
|
|||
// Copyright 2006 The Android Open Source Project
|
||||
|
||||
#ifndef ARMDIS_H
|
||||
#define ARMDIS_H
|
||||
#pragma once
|
||||
|
||||
#include <stdint.h>
|
||||
#include <cstdint>
|
||||
#include <string>
|
||||
|
||||
// Note: this list of opcodes must match the list used to initialize
|
||||
// the opflags[] array in opcode.cpp.
|
||||
|
|
@ -109,38 +109,33 @@ enum Opcode {
|
|||
|
||||
class ARM_Disasm {
|
||||
public:
|
||||
static char *disasm(uint32_t addr, uint32_t insn, char *buffer);
|
||||
static Opcode decode(uint32_t insn);
|
||||
static std::string Disassemble(uint32_t addr, uint32_t insn);
|
||||
static Opcode Decode(uint32_t insn);
|
||||
|
||||
private:
|
||||
static Opcode decode00(uint32_t insn);
|
||||
static Opcode decode01(uint32_t insn);
|
||||
static Opcode decode10(uint32_t insn);
|
||||
static Opcode decode11(uint32_t insn);
|
||||
static Opcode decode_mul(uint32_t insn);
|
||||
static Opcode decode_ldrh(uint32_t insn);
|
||||
static Opcode decode_alu(uint32_t insn);
|
||||
static Opcode Decode00(uint32_t insn);
|
||||
static Opcode Decode01(uint32_t insn);
|
||||
static Opcode Decode10(uint32_t insn);
|
||||
static Opcode Decode11(uint32_t insn);
|
||||
static Opcode DecodeMUL(uint32_t insn);
|
||||
static Opcode DecodeLDRH(uint32_t insn);
|
||||
static Opcode DecodeALU(uint32_t insn);
|
||||
|
||||
static char *disasm_alu(Opcode opcode, uint32_t insn, char *ptr);
|
||||
static char *disasm_branch(uint32_t addr, Opcode opcode, uint32_t insn, char *ptr);
|
||||
static char *disasm_bx(uint32_t insn, char *ptr);
|
||||
static char *disasm_bkpt(uint32_t insn, char *ptr);
|
||||
static char *disasm_clz(uint32_t insn, char *ptr);
|
||||
static char *disasm_memblock(Opcode opcode, uint32_t insn, char *ptr);
|
||||
static char *disasm_mem(uint32_t insn, char *ptr);
|
||||
static char *disasm_memhalf(uint32_t insn, char *ptr);
|
||||
static char *disasm_mcr(Opcode opcode, uint32_t insn, char *ptr);
|
||||
static char *disasm_mla(Opcode opcode, uint32_t insn, char *ptr);
|
||||
static char *disasm_umlal(Opcode opcode, uint32_t insn, char *ptr);
|
||||
static char *disasm_mul(Opcode opcode, uint32_t insn, char *ptr);
|
||||
static char *disasm_mrs(uint32_t insn, char *ptr);
|
||||
static char *disasm_msr(uint32_t insn, char *ptr);
|
||||
static char *disasm_pld(uint32_t insn, char *ptr);
|
||||
static char *disasm_swi(uint32_t insn, char *ptr);
|
||||
static char *disasm_swp(Opcode opcode, uint32_t insn, char *ptr);
|
||||
static std::string DisassembleALU(Opcode opcode, uint32_t insn);
|
||||
static std::string DisassembleBranch(uint32_t addr, Opcode opcode, uint32_t insn);
|
||||
static std::string DisassembleBX(uint32_t insn);
|
||||
static std::string DisassembleBKPT(uint32_t insn);
|
||||
static std::string DisassembleCLZ(uint32_t insn);
|
||||
static std::string DisassembleMemblock(Opcode opcode, uint32_t insn);
|
||||
static std::string DisassembleMem(uint32_t insn);
|
||||
static std::string DisassembleMemHalf(uint32_t insn);
|
||||
static std::string DisassembleMCR(Opcode opcode, uint32_t insn);
|
||||
static std::string DisassembleMLA(Opcode opcode, uint32_t insn);
|
||||
static std::string DisassembleUMLAL(Opcode opcode, uint32_t insn);
|
||||
static std::string DisassembleMUL(Opcode opcode, uint32_t insn);
|
||||
static std::string DisassembleMRS(uint32_t insn);
|
||||
static std::string DisassembleMSR(uint32_t insn);
|
||||
static std::string DisassemblePLD(uint32_t insn);
|
||||
static std::string DisassembleSWI(uint32_t insn);
|
||||
static std::string DisassembleSWP(Opcode opcode, uint32_t insn);
|
||||
};
|
||||
|
||||
extern char *disasm_insn_thumb(uint32_t pc, uint32_t insn1, uint32_t insn2, char *result);
|
||||
extern Opcode decode_insn_thumb(uint32_t given);
|
||||
|
||||
#endif /* ARMDIS_H */
|
||||
|
|
|
|||
|
|
@ -17,6 +17,7 @@
|
|||
|
||||
//#include <util.h>
|
||||
|
||||
#include <string>
|
||||
#include "core/arm/interpreter/armdefs.h"
|
||||
#include "core/arm/interpreter/armemu.h"
|
||||
#include "core/hle/coprocessor.h"
|
||||
|
|
@ -870,12 +871,8 @@ ARMul_CDP (ARMul_State * state, ARMword instr)
|
|||
void
|
||||
ARMul_UndefInstr (ARMul_State * state, ARMword instr)
|
||||
{
|
||||
/*SKYEYE_LOG_IN_CLR(RED, "In %s, line = %d, undef instr: 0x%x\n",
|
||||
__func__, __LINE__, instr);*/
|
||||
char buff[512];
|
||||
ARM_Disasm disasm = ARM_Disasm();
|
||||
disasm.disasm(state->pc, instr, buff);
|
||||
ERROR_LOG(ARM11, "Undefined instruction!! Disasm: %s Opcode: 0x%x", buff, instr);
|
||||
std::string disasm = ARM_Disasm::Disassemble(state->pc, instr);
|
||||
ERROR_LOG(ARM11, "Undefined instruction!! Disasm: %s Opcode: 0x%x", disasm.c_str(), instr);
|
||||
ARMul_Abort (state, ARMul_UndefinedInstrV);
|
||||
}
|
||||
|
||||
|
|
|
|||
Loading…
Reference in a new issue