mirror of
https://github.com/Lime3DS/Lime3DS
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1134 lines
36 KiB
C++
1134 lines
36 KiB
C++
// Copyright 2014 Citra Emulator Project
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// Licensed under GPLv2 or any later version
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// Refer to the license.txt file included.
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#pragma once
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#include <array>
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#include <cstddef>
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#include <initializer_list>
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#include <map>
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#include <vector>
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#include "common/assert.h"
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#include "common/bit_field.h"
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#include "common/common_funcs.h"
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#include "common/common_types.h"
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#include "common/logging/log.h"
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#include "common/vector_math.h"
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namespace Pica {
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// Returns index corresponding to the Regs member labeled by field_name
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// TODO: Due to Visual studio bug 209229, offsetof does not return constant expressions
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// when used with array elements (e.g. PICA_REG_INDEX(vs_uniform_setup.set_value[1])).
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// For details cf. https://connect.microsoft.com/VisualStudio/feedback/details/209229/offsetof-does-not-produce-a-constant-expression-for-array-members
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// Hopefully, this will be fixed sometime in the future.
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// For lack of better alternatives, we currently hardcode the offsets when constant
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// expressions are needed via PICA_REG_INDEX_WORKAROUND (on sane compilers, static_asserts
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// will then make sure the offsets indeed match the automatically calculated ones).
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#define PICA_REG_INDEX(field_name) (offsetof(Pica::Regs, field_name) / sizeof(u32))
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#if defined(_MSC_VER)
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#define PICA_REG_INDEX_WORKAROUND(field_name, backup_workaround_index) (backup_workaround_index)
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#else
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// NOTE: Yeah, hacking in a static_assert here just to workaround the lacking MSVC compiler
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// really is this annoying. This macro just forwards its first argument to PICA_REG_INDEX
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// and then performs a (no-op) cast to size_t iff the second argument matches the expected
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// field offset. Otherwise, the compiler will fail to compile this code.
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#define PICA_REG_INDEX_WORKAROUND(field_name, backup_workaround_index) \
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((typename std::enable_if<backup_workaround_index == PICA_REG_INDEX(field_name), size_t>::type)PICA_REG_INDEX(field_name))
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#endif // _MSC_VER
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struct Regs {
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INSERT_PADDING_WORDS(0x10);
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u32 trigger_irq;
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INSERT_PADDING_WORDS(0x2f);
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enum class CullMode : u32 {
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// Select which polygons are considered to be "frontfacing".
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KeepAll = 0,
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KeepClockWise = 1,
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KeepCounterClockWise = 2,
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// TODO: What does the third value imply?
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};
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union {
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BitField<0, 2, CullMode> cull_mode;
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};
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BitField<0, 24, u32> viewport_size_x;
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INSERT_PADDING_WORDS(0x1);
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BitField<0, 24, u32> viewport_size_y;
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INSERT_PADDING_WORDS(0x9);
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BitField<0, 24, u32> viewport_depth_range; // float24
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BitField<0, 24, u32> viewport_depth_far_plane; // float24
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INSERT_PADDING_WORDS(0x1);
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union VSOutputAttributes {
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// Maps components of output vertex attributes to semantics
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enum Semantic : u32
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{
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POSITION_X = 0,
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POSITION_Y = 1,
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POSITION_Z = 2,
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POSITION_W = 3,
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COLOR_R = 8,
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COLOR_G = 9,
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COLOR_B = 10,
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COLOR_A = 11,
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TEXCOORD0_U = 12,
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TEXCOORD0_V = 13,
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TEXCOORD1_U = 14,
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TEXCOORD1_V = 15,
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TEXCOORD2_U = 22,
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TEXCOORD2_V = 23,
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INVALID = 31,
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};
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BitField< 0, 5, Semantic> map_x;
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BitField< 8, 5, Semantic> map_y;
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BitField<16, 5, Semantic> map_z;
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BitField<24, 5, Semantic> map_w;
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} vs_output_attributes[7];
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INSERT_PADDING_WORDS(0x11);
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union {
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BitField< 0, 16, u32> x;
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BitField<16, 16, u32> y;
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} viewport_corner;
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INSERT_PADDING_WORDS(0x17);
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struct TextureConfig {
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enum WrapMode : u32 {
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ClampToEdge = 0,
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Repeat = 2,
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MirroredRepeat = 3,
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};
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INSERT_PADDING_WORDS(0x1);
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union {
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BitField< 0, 16, u32> height;
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BitField<16, 16, u32> width;
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};
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union {
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BitField< 8, 2, WrapMode> wrap_s;
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BitField<12, 2, WrapMode> wrap_t;
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};
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INSERT_PADDING_WORDS(0x1);
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u32 address;
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u32 GetPhysicalAddress() const {
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return DecodeAddressRegister(address);
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}
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// texture1 and texture2 store the texture format directly after the address
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// whereas texture0 inserts some additional flags inbetween.
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// Hence, we store the format separately so that all other parameters can be described
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// in a single structure.
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};
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enum class TextureFormat : u32 {
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RGBA8 = 0,
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RGB8 = 1,
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RGB5A1 = 2,
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RGB565 = 3,
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RGBA4 = 4,
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IA8 = 5,
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I8 = 7,
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A8 = 8,
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IA4 = 9,
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I4 = 10,
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A4 = 11,
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ETC1 = 12, // compressed
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ETC1A4 = 13, // compressed
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};
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enum class LogicOp : u32 {
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Clear = 0,
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And = 1,
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AndReverse = 2,
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Copy = 3,
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Set = 4,
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CopyInverted = 5,
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NoOp = 6,
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Invert = 7,
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Nand = 8,
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Or = 9,
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Nor = 10,
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Xor = 11,
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Equiv = 12,
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AndInverted = 13,
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OrReverse = 14,
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OrInverted = 15,
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};
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static unsigned NibblesPerPixel(TextureFormat format) {
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switch (format) {
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case TextureFormat::RGBA8:
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return 8;
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case TextureFormat::RGB8:
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return 6;
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case TextureFormat::RGB5A1:
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case TextureFormat::RGB565:
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case TextureFormat::RGBA4:
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case TextureFormat::IA8:
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return 4;
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case TextureFormat::A4:
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return 1;
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case TextureFormat::I8:
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case TextureFormat::A8:
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case TextureFormat::IA4:
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default: // placeholder for yet unknown formats
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return 2;
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}
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}
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union {
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BitField< 0, 1, u32> texture0_enable;
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BitField< 1, 1, u32> texture1_enable;
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BitField< 2, 1, u32> texture2_enable;
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};
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TextureConfig texture0;
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INSERT_PADDING_WORDS(0x8);
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BitField<0, 4, TextureFormat> texture0_format;
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INSERT_PADDING_WORDS(0x2);
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TextureConfig texture1;
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BitField<0, 4, TextureFormat> texture1_format;
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INSERT_PADDING_WORDS(0x2);
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TextureConfig texture2;
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BitField<0, 4, TextureFormat> texture2_format;
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INSERT_PADDING_WORDS(0x21);
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struct FullTextureConfig {
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const bool enabled;
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const TextureConfig config;
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const TextureFormat format;
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};
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const std::array<FullTextureConfig, 3> GetTextures() const {
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return {{
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{ texture0_enable.ToBool(), texture0, texture0_format },
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{ texture1_enable.ToBool(), texture1, texture1_format },
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{ texture2_enable.ToBool(), texture2, texture2_format }
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}};
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}
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// 0xc0-0xff: Texture Combiner (akin to glTexEnv)
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struct TevStageConfig {
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enum class Source : u32 {
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PrimaryColor = 0x0,
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PrimaryFragmentColor = 0x1,
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SecondaryFragmentColor = 0x2,
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Texture0 = 0x3,
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Texture1 = 0x4,
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Texture2 = 0x5,
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Texture3 = 0x6,
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PreviousBuffer = 0xd,
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Constant = 0xe,
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Previous = 0xf,
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};
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enum class ColorModifier : u32 {
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SourceColor = 0x0,
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OneMinusSourceColor = 0x1,
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SourceAlpha = 0x2,
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OneMinusSourceAlpha = 0x3,
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SourceRed = 0x4,
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OneMinusSourceRed = 0x5,
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SourceGreen = 0x8,
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OneMinusSourceGreen = 0x9,
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SourceBlue = 0xc,
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OneMinusSourceBlue = 0xd,
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};
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enum class AlphaModifier : u32 {
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SourceAlpha = 0x0,
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OneMinusSourceAlpha = 0x1,
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SourceRed = 0x2,
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OneMinusSourceRed = 0x3,
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SourceGreen = 0x4,
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OneMinusSourceGreen = 0x5,
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SourceBlue = 0x6,
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OneMinusSourceBlue = 0x7,
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};
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enum class Operation : u32 {
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Replace = 0,
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Modulate = 1,
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Add = 2,
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AddSigned = 3,
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Lerp = 4,
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Subtract = 5,
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MultiplyThenAdd = 8,
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AddThenMultiply = 9,
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};
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union {
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BitField< 0, 4, Source> color_source1;
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BitField< 4, 4, Source> color_source2;
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BitField< 8, 4, Source> color_source3;
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BitField<16, 4, Source> alpha_source1;
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BitField<20, 4, Source> alpha_source2;
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BitField<24, 4, Source> alpha_source3;
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};
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union {
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BitField< 0, 4, ColorModifier> color_modifier1;
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BitField< 4, 4, ColorModifier> color_modifier2;
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BitField< 8, 4, ColorModifier> color_modifier3;
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BitField<12, 3, AlphaModifier> alpha_modifier1;
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BitField<16, 3, AlphaModifier> alpha_modifier2;
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BitField<20, 3, AlphaModifier> alpha_modifier3;
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};
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union {
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BitField< 0, 4, Operation> color_op;
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BitField<16, 4, Operation> alpha_op;
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};
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union {
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BitField< 0, 8, u32> const_r;
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BitField< 8, 8, u32> const_g;
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BitField<16, 8, u32> const_b;
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BitField<24, 8, u32> const_a;
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};
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union {
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BitField< 0, 2, u32> color_scale;
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BitField<16, 2, u32> alpha_scale;
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};
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inline unsigned GetColorMultiplier() const {
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return (color_scale < 3) ? (1 << color_scale) : 1;
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}
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inline unsigned GetAlphaMultiplier() const {
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return (alpha_scale < 3) ? (1 << alpha_scale) : 1;
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}
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};
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TevStageConfig tev_stage0;
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INSERT_PADDING_WORDS(0x3);
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TevStageConfig tev_stage1;
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INSERT_PADDING_WORDS(0x3);
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TevStageConfig tev_stage2;
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INSERT_PADDING_WORDS(0x3);
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TevStageConfig tev_stage3;
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INSERT_PADDING_WORDS(0x3);
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union {
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// Tev stages 0-3 write their output to the combiner buffer if the corresponding bit in
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// these masks are set
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BitField< 8, 4, u32> update_mask_rgb;
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BitField<12, 4, u32> update_mask_a;
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bool TevStageUpdatesCombinerBufferColor(unsigned stage_index) const {
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return (stage_index < 4) && (update_mask_rgb & (1 << stage_index));
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}
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bool TevStageUpdatesCombinerBufferAlpha(unsigned stage_index) const {
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return (stage_index < 4) && (update_mask_a & (1 << stage_index));
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}
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} tev_combiner_buffer_input;
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INSERT_PADDING_WORDS(0xf);
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TevStageConfig tev_stage4;
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INSERT_PADDING_WORDS(0x3);
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TevStageConfig tev_stage5;
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union {
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BitField< 0, 8, u32> r;
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BitField< 8, 8, u32> g;
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BitField<16, 8, u32> b;
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BitField<24, 8, u32> a;
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} tev_combiner_buffer_color;
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INSERT_PADDING_WORDS(0x2);
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const std::array<Regs::TevStageConfig,6> GetTevStages() const {
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return {{ tev_stage0, tev_stage1,
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tev_stage2, tev_stage3,
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tev_stage4, tev_stage5 }};
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};
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enum class BlendEquation : u32 {
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Add = 0,
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Subtract = 1,
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ReverseSubtract = 2,
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Min = 3,
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Max = 4,
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};
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enum class BlendFactor : u32 {
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Zero = 0,
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One = 1,
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SourceColor = 2,
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OneMinusSourceColor = 3,
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DestColor = 4,
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OneMinusDestColor = 5,
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SourceAlpha = 6,
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OneMinusSourceAlpha = 7,
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DestAlpha = 8,
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OneMinusDestAlpha = 9,
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ConstantColor = 10,
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OneMinusConstantColor = 11,
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ConstantAlpha = 12,
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OneMinusConstantAlpha = 13,
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SourceAlphaSaturate = 14,
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};
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enum class CompareFunc : u32 {
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Never = 0,
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Always = 1,
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Equal = 2,
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NotEqual = 3,
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LessThan = 4,
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LessThanOrEqual = 5,
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GreaterThan = 6,
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GreaterThanOrEqual = 7,
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};
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struct {
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union {
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// If false, logic blending is used
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BitField<8, 1, u32> alphablend_enable;
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};
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union {
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BitField< 0, 8, BlendEquation> blend_equation_rgb;
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BitField< 8, 8, BlendEquation> blend_equation_a;
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BitField<16, 4, BlendFactor> factor_source_rgb;
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BitField<20, 4, BlendFactor> factor_dest_rgb;
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BitField<24, 4, BlendFactor> factor_source_a;
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BitField<28, 4, BlendFactor> factor_dest_a;
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} alpha_blending;
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union {
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BitField<0, 4, LogicOp> logic_op;
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};
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union {
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BitField< 0, 8, u32> r;
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BitField< 8, 8, u32> g;
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BitField<16, 8, u32> b;
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BitField<24, 8, u32> a;
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} blend_const;
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union {
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BitField< 0, 1, u32> enable;
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BitField< 4, 3, CompareFunc> func;
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BitField< 8, 8, u32> ref;
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} alpha_test;
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union {
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BitField< 0, 1, u32> stencil_test_enable;
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BitField< 4, 3, CompareFunc> stencil_test_func;
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BitField< 8, 8, u32> stencil_replacement_value;
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BitField<16, 8, u32> stencil_reference_value;
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BitField<24, 8, u32> stencil_mask;
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} stencil_test;
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INSERT_PADDING_WORDS(0x1);
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union {
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BitField< 0, 1, u32> depth_test_enable;
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BitField< 4, 3, CompareFunc> depth_test_func;
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BitField< 8, 1, u32> red_enable;
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BitField< 9, 1, u32> green_enable;
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BitField<10, 1, u32> blue_enable;
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BitField<11, 1, u32> alpha_enable;
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BitField<12, 1, u32> depth_write_enable;
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};
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INSERT_PADDING_WORDS(0x8);
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} output_merger;
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// Components are laid out in reverse byte order, most significant bits first.
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enum class ColorFormat : u32 {
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RGBA8 = 0,
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RGB8 = 1,
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RGB5A1 = 2,
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RGB565 = 3,
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RGBA4 = 4,
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};
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enum class DepthFormat : u32 {
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D16 = 0,
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D24 = 2,
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D24S8 = 3,
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};
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// Returns the number of bytes in the specified color format
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static unsigned BytesPerColorPixel(ColorFormat format) {
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switch (format) {
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case ColorFormat::RGBA8:
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return 4;
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case ColorFormat::RGB8:
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return 3;
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case ColorFormat::RGB5A1:
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case ColorFormat::RGB565:
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case ColorFormat::RGBA4:
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return 2;
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default:
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LOG_CRITICAL(HW_GPU, "Unknown color format %u", format);
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UNIMPLEMENTED();
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}
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}
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struct {
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INSERT_PADDING_WORDS(0x6);
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DepthFormat depth_format;
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BitField<16, 3, ColorFormat> color_format;
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INSERT_PADDING_WORDS(0x4);
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u32 depth_buffer_address;
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u32 color_buffer_address;
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union {
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// Apparently, the framebuffer width is stored as expected,
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// while the height is stored as the actual height minus one.
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// Hence, don't access these fields directly but use the accessors
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// GetWidth() and GetHeight() instead.
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BitField< 0, 11, u32> width;
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BitField<12, 10, u32> height;
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};
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INSERT_PADDING_WORDS(0x1);
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inline u32 GetColorBufferPhysicalAddress() const {
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return DecodeAddressRegister(color_buffer_address);
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}
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inline u32 GetDepthBufferPhysicalAddress() const {
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return DecodeAddressRegister(depth_buffer_address);
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}
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inline u32 GetWidth() const {
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return width;
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}
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inline u32 GetHeight() const {
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return height + 1;
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}
|
|
} framebuffer;
|
|
|
|
// Returns the number of bytes in the specified depth format
|
|
static u32 BytesPerDepthPixel(DepthFormat format) {
|
|
switch (format) {
|
|
case DepthFormat::D16:
|
|
return 2;
|
|
case DepthFormat::D24:
|
|
return 3;
|
|
case DepthFormat::D24S8:
|
|
return 4;
|
|
default:
|
|
LOG_CRITICAL(HW_GPU, "Unknown depth format %u", format);
|
|
UNIMPLEMENTED();
|
|
}
|
|
}
|
|
|
|
// Returns the number of bits per depth component of the specified depth format
|
|
static u32 DepthBitsPerPixel(DepthFormat format) {
|
|
switch (format) {
|
|
case DepthFormat::D16:
|
|
return 16;
|
|
case DepthFormat::D24:
|
|
case DepthFormat::D24S8:
|
|
return 24;
|
|
default:
|
|
LOG_CRITICAL(HW_GPU, "Unknown depth format %u", format);
|
|
UNIMPLEMENTED();
|
|
}
|
|
}
|
|
|
|
INSERT_PADDING_WORDS(0xe0);
|
|
|
|
enum class VertexAttributeFormat : u64 {
|
|
BYTE = 0,
|
|
UBYTE = 1,
|
|
SHORT = 2,
|
|
FLOAT = 3,
|
|
};
|
|
|
|
struct {
|
|
BitField<0, 29, u32> base_address;
|
|
|
|
u32 GetPhysicalBaseAddress() const {
|
|
return DecodeAddressRegister(base_address);
|
|
}
|
|
|
|
// Descriptor for internal vertex attributes
|
|
union {
|
|
BitField< 0, 2, VertexAttributeFormat> format0; // size of one element
|
|
BitField< 2, 2, u64> size0; // number of elements minus 1
|
|
BitField< 4, 2, VertexAttributeFormat> format1;
|
|
BitField< 6, 2, u64> size1;
|
|
BitField< 8, 2, VertexAttributeFormat> format2;
|
|
BitField<10, 2, u64> size2;
|
|
BitField<12, 2, VertexAttributeFormat> format3;
|
|
BitField<14, 2, u64> size3;
|
|
BitField<16, 2, VertexAttributeFormat> format4;
|
|
BitField<18, 2, u64> size4;
|
|
BitField<20, 2, VertexAttributeFormat> format5;
|
|
BitField<22, 2, u64> size5;
|
|
BitField<24, 2, VertexAttributeFormat> format6;
|
|
BitField<26, 2, u64> size6;
|
|
BitField<28, 2, VertexAttributeFormat> format7;
|
|
BitField<30, 2, u64> size7;
|
|
BitField<32, 2, VertexAttributeFormat> format8;
|
|
BitField<34, 2, u64> size8;
|
|
BitField<36, 2, VertexAttributeFormat> format9;
|
|
BitField<38, 2, u64> size9;
|
|
BitField<40, 2, VertexAttributeFormat> format10;
|
|
BitField<42, 2, u64> size10;
|
|
BitField<44, 2, VertexAttributeFormat> format11;
|
|
BitField<46, 2, u64> size11;
|
|
|
|
BitField<48, 12, u64> attribute_mask;
|
|
|
|
// number of total attributes minus 1
|
|
BitField<60, 4, u64> num_extra_attributes;
|
|
};
|
|
|
|
inline VertexAttributeFormat GetFormat(int n) const {
|
|
VertexAttributeFormat formats[] = {
|
|
format0, format1, format2, format3,
|
|
format4, format5, format6, format7,
|
|
format8, format9, format10, format11
|
|
};
|
|
return formats[n];
|
|
}
|
|
|
|
inline int GetNumElements(int n) const {
|
|
u64 sizes[] = {
|
|
size0, size1, size2, size3,
|
|
size4, size5, size6, size7,
|
|
size8, size9, size10, size11
|
|
};
|
|
return (int)sizes[n]+1;
|
|
}
|
|
|
|
inline int GetElementSizeInBytes(int n) const {
|
|
return (GetFormat(n) == VertexAttributeFormat::FLOAT) ? 4 :
|
|
(GetFormat(n) == VertexAttributeFormat::SHORT) ? 2 : 1;
|
|
}
|
|
|
|
inline int GetStride(int n) const {
|
|
return GetNumElements(n) * GetElementSizeInBytes(n);
|
|
}
|
|
|
|
inline bool IsDefaultAttribute(int id) const {
|
|
return (id >= 12) || (attribute_mask & (1ULL << id)) != 0;
|
|
}
|
|
|
|
inline int GetNumTotalAttributes() const {
|
|
return (int)num_extra_attributes+1;
|
|
}
|
|
|
|
// Attribute loaders map the source vertex data to input attributes
|
|
// This e.g. allows to load different attributes from different memory locations
|
|
struct {
|
|
// Source attribute data offset from the base address
|
|
u32 data_offset;
|
|
|
|
union {
|
|
BitField< 0, 4, u64> comp0;
|
|
BitField< 4, 4, u64> comp1;
|
|
BitField< 8, 4, u64> comp2;
|
|
BitField<12, 4, u64> comp3;
|
|
BitField<16, 4, u64> comp4;
|
|
BitField<20, 4, u64> comp5;
|
|
BitField<24, 4, u64> comp6;
|
|
BitField<28, 4, u64> comp7;
|
|
BitField<32, 4, u64> comp8;
|
|
BitField<36, 4, u64> comp9;
|
|
BitField<40, 4, u64> comp10;
|
|
BitField<44, 4, u64> comp11;
|
|
|
|
// bytes for a single vertex in this loader
|
|
BitField<48, 8, u64> byte_count;
|
|
|
|
BitField<60, 4, u64> component_count;
|
|
};
|
|
|
|
inline int GetComponent(int n) const {
|
|
u64 components[] = {
|
|
comp0, comp1, comp2, comp3,
|
|
comp4, comp5, comp6, comp7,
|
|
comp8, comp9, comp10, comp11
|
|
};
|
|
return (int)components[n];
|
|
}
|
|
} attribute_loaders[12];
|
|
} vertex_attributes;
|
|
|
|
struct {
|
|
enum IndexFormat : u32 {
|
|
BYTE = 0,
|
|
SHORT = 1,
|
|
};
|
|
|
|
union {
|
|
BitField<0, 31, u32> offset; // relative to base attribute address
|
|
BitField<31, 1, IndexFormat> format;
|
|
};
|
|
} index_array;
|
|
|
|
// Number of vertices to render
|
|
u32 num_vertices;
|
|
|
|
INSERT_PADDING_WORDS(0x5);
|
|
|
|
// These two trigger rendering of triangles
|
|
u32 trigger_draw;
|
|
u32 trigger_draw_indexed;
|
|
|
|
INSERT_PADDING_WORDS(0x2);
|
|
|
|
// These registers are used to setup the default "fall-back" vertex shader attributes
|
|
struct {
|
|
// Index of the current default attribute
|
|
u32 index;
|
|
|
|
// Writing to these registers sets the "current" default attribute.
|
|
u32 set_value[3];
|
|
} vs_default_attributes_setup;
|
|
|
|
INSERT_PADDING_WORDS(0x2);
|
|
|
|
struct {
|
|
// There are two channels that can be used to configure the next command buffer, which
|
|
// can be then executed by writing to the "trigger" registers. There are two reasons why a
|
|
// game might use this feature:
|
|
// 1) With this, an arbitrary number of additional command buffers may be executed in
|
|
// sequence without requiring any intervention of the CPU after the initial one is
|
|
// kicked off.
|
|
// 2) Games can configure these registers to provide a command list subroutine mechanism.
|
|
|
|
BitField< 0, 20, u32> size[2]; ///< Size (in bytes / 8) of each channel's command buffer
|
|
BitField< 0, 28, u32> addr[2]; ///< Physical address / 8 of each channel's command buffer
|
|
u32 trigger[2]; ///< Triggers execution of the channel's command buffer when written to
|
|
|
|
unsigned GetSize(unsigned index) const {
|
|
ASSERT(index < 2);
|
|
return 8 * size[index];
|
|
}
|
|
|
|
PAddr GetPhysicalAddress(unsigned index) const {
|
|
ASSERT(index < 2);
|
|
return (PAddr)(8 * addr[index]);
|
|
}
|
|
} command_buffer;
|
|
|
|
INSERT_PADDING_WORDS(0x20);
|
|
|
|
enum class TriangleTopology : u32 {
|
|
List = 0,
|
|
Strip = 1,
|
|
Fan = 2,
|
|
ListIndexed = 3, // TODO: No idea if this is correct
|
|
};
|
|
|
|
BitField<8, 2, TriangleTopology> triangle_topology;
|
|
|
|
INSERT_PADDING_WORDS(0x51);
|
|
|
|
BitField<0, 16, u32> vs_bool_uniforms;
|
|
union {
|
|
BitField< 0, 8, u32> x;
|
|
BitField< 8, 8, u32> y;
|
|
BitField<16, 8, u32> z;
|
|
BitField<24, 8, u32> w;
|
|
} vs_int_uniforms[4];
|
|
|
|
INSERT_PADDING_WORDS(0x5);
|
|
|
|
// Offset to shader program entry point (in words)
|
|
BitField<0, 16, u32> vs_main_offset;
|
|
|
|
union {
|
|
BitField< 0, 4, u64> attribute0_register;
|
|
BitField< 4, 4, u64> attribute1_register;
|
|
BitField< 8, 4, u64> attribute2_register;
|
|
BitField<12, 4, u64> attribute3_register;
|
|
BitField<16, 4, u64> attribute4_register;
|
|
BitField<20, 4, u64> attribute5_register;
|
|
BitField<24, 4, u64> attribute6_register;
|
|
BitField<28, 4, u64> attribute7_register;
|
|
BitField<32, 4, u64> attribute8_register;
|
|
BitField<36, 4, u64> attribute9_register;
|
|
BitField<40, 4, u64> attribute10_register;
|
|
BitField<44, 4, u64> attribute11_register;
|
|
BitField<48, 4, u64> attribute12_register;
|
|
BitField<52, 4, u64> attribute13_register;
|
|
BitField<56, 4, u64> attribute14_register;
|
|
BitField<60, 4, u64> attribute15_register;
|
|
|
|
int GetRegisterForAttribute(int attribute_index) const {
|
|
u64 fields[] = {
|
|
attribute0_register, attribute1_register, attribute2_register, attribute3_register,
|
|
attribute4_register, attribute5_register, attribute6_register, attribute7_register,
|
|
attribute8_register, attribute9_register, attribute10_register, attribute11_register,
|
|
attribute12_register, attribute13_register, attribute14_register, attribute15_register,
|
|
};
|
|
return (int)fields[attribute_index];
|
|
}
|
|
} vs_input_register_map;
|
|
|
|
INSERT_PADDING_WORDS(0x3);
|
|
|
|
struct {
|
|
enum Format : u32
|
|
{
|
|
FLOAT24 = 0,
|
|
FLOAT32 = 1
|
|
};
|
|
|
|
bool IsFloat32() const {
|
|
return format == FLOAT32;
|
|
}
|
|
|
|
union {
|
|
// Index of the next uniform to write to
|
|
// TODO: ctrulib uses 8 bits for this, however that seems to yield lots of invalid indices
|
|
BitField<0, 7, u32> index;
|
|
|
|
BitField<31, 1, Format> format;
|
|
};
|
|
|
|
// Writing to these registers sets the "current" uniform.
|
|
// TODO: It's not clear how the hardware stores what the "current" uniform is.
|
|
u32 set_value[8];
|
|
|
|
} vs_uniform_setup;
|
|
|
|
INSERT_PADDING_WORDS(0x2);
|
|
|
|
struct {
|
|
// Offset of the next instruction to write code to.
|
|
// Incremented with each instruction write.
|
|
u32 offset;
|
|
|
|
// Writing to these registers sets the "current" word in the shader program.
|
|
// TODO: It's not clear how the hardware stores what the "current" word is.
|
|
u32 set_word[8];
|
|
} vs_program;
|
|
|
|
INSERT_PADDING_WORDS(0x1);
|
|
|
|
// This register group is used to load an internal table of swizzling patterns,
|
|
// which are indexed by each shader instruction to specify vector component swizzling.
|
|
struct {
|
|
// Offset of the next swizzle pattern to write code to.
|
|
// Incremented with each instruction write.
|
|
u32 offset;
|
|
|
|
// Writing to these registers sets the "current" swizzle pattern in the table.
|
|
// TODO: It's not clear how the hardware stores what the "current" swizzle pattern is.
|
|
u32 set_word[8];
|
|
} vs_swizzle_patterns;
|
|
|
|
INSERT_PADDING_WORDS(0x22);
|
|
|
|
// Map register indices to names readable by humans
|
|
// Used for debugging purposes, so performance is not an issue here
|
|
static std::string GetCommandName(int index) {
|
|
std::map<u32, std::string> map;
|
|
|
|
#define ADD_FIELD(name) \
|
|
do { \
|
|
map.insert({PICA_REG_INDEX(name), #name}); \
|
|
/* TODO: change to Regs::name when VS2015 and other compilers support it */ \
|
|
for (u32 i = PICA_REG_INDEX(name) + 1; i < PICA_REG_INDEX(name) + sizeof(Regs().name) / 4; ++i) \
|
|
map.insert({i, #name + std::string("+") + std::to_string(i-PICA_REG_INDEX(name))}); \
|
|
} while(false)
|
|
|
|
ADD_FIELD(trigger_irq);
|
|
ADD_FIELD(cull_mode);
|
|
ADD_FIELD(viewport_size_x);
|
|
ADD_FIELD(viewport_size_y);
|
|
ADD_FIELD(viewport_depth_range);
|
|
ADD_FIELD(viewport_depth_far_plane);
|
|
ADD_FIELD(viewport_corner);
|
|
ADD_FIELD(texture0_enable);
|
|
ADD_FIELD(texture0);
|
|
ADD_FIELD(texture0_format);
|
|
ADD_FIELD(texture1);
|
|
ADD_FIELD(texture1_format);
|
|
ADD_FIELD(texture2);
|
|
ADD_FIELD(texture2_format);
|
|
ADD_FIELD(tev_stage0);
|
|
ADD_FIELD(tev_stage1);
|
|
ADD_FIELD(tev_stage2);
|
|
ADD_FIELD(tev_stage3);
|
|
ADD_FIELD(tev_combiner_buffer_input);
|
|
ADD_FIELD(tev_stage4);
|
|
ADD_FIELD(tev_stage5);
|
|
ADD_FIELD(tev_combiner_buffer_color);
|
|
ADD_FIELD(output_merger);
|
|
ADD_FIELD(framebuffer);
|
|
ADD_FIELD(vertex_attributes);
|
|
ADD_FIELD(index_array);
|
|
ADD_FIELD(num_vertices);
|
|
ADD_FIELD(trigger_draw);
|
|
ADD_FIELD(trigger_draw_indexed);
|
|
ADD_FIELD(vs_default_attributes_setup);
|
|
ADD_FIELD(command_buffer);
|
|
ADD_FIELD(triangle_topology);
|
|
ADD_FIELD(vs_bool_uniforms);
|
|
ADD_FIELD(vs_int_uniforms);
|
|
ADD_FIELD(vs_main_offset);
|
|
ADD_FIELD(vs_input_register_map);
|
|
ADD_FIELD(vs_uniform_setup);
|
|
ADD_FIELD(vs_program);
|
|
ADD_FIELD(vs_swizzle_patterns);
|
|
|
|
#undef ADD_FIELD
|
|
|
|
// Return empty string if no match is found
|
|
return map[index];
|
|
}
|
|
|
|
static inline size_t NumIds() {
|
|
return sizeof(Regs) / sizeof(u32);
|
|
}
|
|
|
|
u32& operator [] (int index) const {
|
|
u32* content = (u32*)this;
|
|
return content[index];
|
|
}
|
|
|
|
u32& operator [] (int index) {
|
|
u32* content = (u32*)this;
|
|
return content[index];
|
|
}
|
|
|
|
private:
|
|
/*
|
|
* Most physical addresses which Pica registers refer to are 8-byte aligned.
|
|
* This function should be used to get the address from a raw register value.
|
|
*/
|
|
static inline u32 DecodeAddressRegister(u32 register_value) {
|
|
return register_value * 8;
|
|
}
|
|
};
|
|
|
|
// TODO: MSVC does not support using offsetof() on non-static data members even though this
|
|
// is technically allowed since C++11. This macro should be enabled once MSVC adds
|
|
// support for that.
|
|
#ifndef _MSC_VER
|
|
#define ASSERT_REG_POSITION(field_name, position) static_assert(offsetof(Regs, field_name) == position * 4, "Field "#field_name" has invalid position")
|
|
|
|
ASSERT_REG_POSITION(trigger_irq, 0x10);
|
|
ASSERT_REG_POSITION(cull_mode, 0x40);
|
|
ASSERT_REG_POSITION(viewport_size_x, 0x41);
|
|
ASSERT_REG_POSITION(viewport_size_y, 0x43);
|
|
ASSERT_REG_POSITION(viewport_depth_range, 0x4d);
|
|
ASSERT_REG_POSITION(viewport_depth_far_plane, 0x4e);
|
|
ASSERT_REG_POSITION(vs_output_attributes[0], 0x50);
|
|
ASSERT_REG_POSITION(vs_output_attributes[1], 0x51);
|
|
ASSERT_REG_POSITION(viewport_corner, 0x68);
|
|
ASSERT_REG_POSITION(texture0_enable, 0x80);
|
|
ASSERT_REG_POSITION(texture0, 0x81);
|
|
ASSERT_REG_POSITION(texture0_format, 0x8e);
|
|
ASSERT_REG_POSITION(texture1, 0x91);
|
|
ASSERT_REG_POSITION(texture1_format, 0x96);
|
|
ASSERT_REG_POSITION(texture2, 0x99);
|
|
ASSERT_REG_POSITION(texture2_format, 0x9e);
|
|
ASSERT_REG_POSITION(tev_stage0, 0xc0);
|
|
ASSERT_REG_POSITION(tev_stage1, 0xc8);
|
|
ASSERT_REG_POSITION(tev_stage2, 0xd0);
|
|
ASSERT_REG_POSITION(tev_stage3, 0xd8);
|
|
ASSERT_REG_POSITION(tev_combiner_buffer_input, 0xe0);
|
|
ASSERT_REG_POSITION(tev_stage4, 0xf0);
|
|
ASSERT_REG_POSITION(tev_stage5, 0xf8);
|
|
ASSERT_REG_POSITION(tev_combiner_buffer_color, 0xfd);
|
|
ASSERT_REG_POSITION(output_merger, 0x100);
|
|
ASSERT_REG_POSITION(framebuffer, 0x110);
|
|
ASSERT_REG_POSITION(vertex_attributes, 0x200);
|
|
ASSERT_REG_POSITION(index_array, 0x227);
|
|
ASSERT_REG_POSITION(num_vertices, 0x228);
|
|
ASSERT_REG_POSITION(trigger_draw, 0x22e);
|
|
ASSERT_REG_POSITION(trigger_draw_indexed, 0x22f);
|
|
ASSERT_REG_POSITION(vs_default_attributes_setup, 0x232);
|
|
ASSERT_REG_POSITION(command_buffer, 0x238);
|
|
ASSERT_REG_POSITION(triangle_topology, 0x25e);
|
|
ASSERT_REG_POSITION(vs_bool_uniforms, 0x2b0);
|
|
ASSERT_REG_POSITION(vs_int_uniforms, 0x2b1);
|
|
ASSERT_REG_POSITION(vs_main_offset, 0x2ba);
|
|
ASSERT_REG_POSITION(vs_input_register_map, 0x2bb);
|
|
ASSERT_REG_POSITION(vs_uniform_setup, 0x2c0);
|
|
ASSERT_REG_POSITION(vs_program, 0x2cb);
|
|
ASSERT_REG_POSITION(vs_swizzle_patterns, 0x2d5);
|
|
|
|
#undef ASSERT_REG_POSITION
|
|
#endif // !defined(_MSC_VER)
|
|
|
|
// The total number of registers is chosen arbitrarily, but let's make sure it's not some odd value anyway.
|
|
static_assert(sizeof(Regs) <= 0x300 * sizeof(u32), "Register set structure larger than it should be");
|
|
static_assert(sizeof(Regs) >= 0x300 * sizeof(u32), "Register set structure smaller than it should be");
|
|
|
|
struct float24 {
|
|
static float24 FromFloat32(float val) {
|
|
float24 ret;
|
|
ret.value = val;
|
|
return ret;
|
|
}
|
|
|
|
// 16 bit mantissa, 7 bit exponent, 1 bit sign
|
|
// TODO: No idea if this works as intended
|
|
static float24 FromRawFloat24(u32 hex) {
|
|
float24 ret;
|
|
if ((hex & 0xFFFFFF) == 0) {
|
|
ret.value = 0;
|
|
} else {
|
|
u32 mantissa = hex & 0xFFFF;
|
|
u32 exponent = (hex >> 16) & 0x7F;
|
|
u32 sign = hex >> 23;
|
|
ret.value = powf(2.0f, (float)exponent-63.0f) * (1.0f + mantissa * powf(2.0f, -16.f));
|
|
if (sign)
|
|
ret.value = -ret.value;
|
|
}
|
|
return ret;
|
|
}
|
|
|
|
// Not recommended for anything but logging
|
|
float ToFloat32() const {
|
|
return value;
|
|
}
|
|
|
|
float24 operator * (const float24& flt) const {
|
|
return float24::FromFloat32(ToFloat32() * flt.ToFloat32());
|
|
}
|
|
|
|
float24 operator / (const float24& flt) const {
|
|
return float24::FromFloat32(ToFloat32() / flt.ToFloat32());
|
|
}
|
|
|
|
float24 operator + (const float24& flt) const {
|
|
return float24::FromFloat32(ToFloat32() + flt.ToFloat32());
|
|
}
|
|
|
|
float24 operator - (const float24& flt) const {
|
|
return float24::FromFloat32(ToFloat32() - flt.ToFloat32());
|
|
}
|
|
|
|
float24& operator *= (const float24& flt) {
|
|
value *= flt.ToFloat32();
|
|
return *this;
|
|
}
|
|
|
|
float24& operator /= (const float24& flt) {
|
|
value /= flt.ToFloat32();
|
|
return *this;
|
|
}
|
|
|
|
float24& operator += (const float24& flt) {
|
|
value += flt.ToFloat32();
|
|
return *this;
|
|
}
|
|
|
|
float24& operator -= (const float24& flt) {
|
|
value -= flt.ToFloat32();
|
|
return *this;
|
|
}
|
|
|
|
float24 operator - () const {
|
|
return float24::FromFloat32(-ToFloat32());
|
|
}
|
|
|
|
bool operator < (const float24& flt) const {
|
|
return ToFloat32() < flt.ToFloat32();
|
|
}
|
|
|
|
bool operator > (const float24& flt) const {
|
|
return ToFloat32() > flt.ToFloat32();
|
|
}
|
|
|
|
bool operator >= (const float24& flt) const {
|
|
return ToFloat32() >= flt.ToFloat32();
|
|
}
|
|
|
|
bool operator <= (const float24& flt) const {
|
|
return ToFloat32() <= flt.ToFloat32();
|
|
}
|
|
|
|
bool operator == (const float24& flt) const {
|
|
return ToFloat32() == flt.ToFloat32();
|
|
}
|
|
|
|
bool operator != (const float24& flt) const {
|
|
return ToFloat32() != flt.ToFloat32();
|
|
}
|
|
|
|
private:
|
|
// Stored as a regular float, merely for convenience
|
|
// TODO: Perform proper arithmetic on this!
|
|
float value;
|
|
};
|
|
|
|
/// Struct used to describe current Pica state
|
|
struct State {
|
|
/// Pica registers
|
|
Regs regs;
|
|
|
|
/// Vertex shader memory
|
|
struct {
|
|
struct {
|
|
Math::Vec4<float24> f[96];
|
|
std::array<bool, 16> b;
|
|
std::array<Math::Vec4<u8>, 4> i;
|
|
} uniforms;
|
|
|
|
Math::Vec4<float24> default_attributes[16];
|
|
|
|
std::array<u32, 1024> program_code;
|
|
std::array<u32, 1024> swizzle_data;
|
|
} vs;
|
|
|
|
/// Current Pica command list
|
|
struct {
|
|
const u32* head_ptr;
|
|
const u32* current_ptr;
|
|
u32 length;
|
|
} cmd_list;
|
|
};
|
|
|
|
/// Initialize Pica state
|
|
void Init();
|
|
|
|
/// Shutdown Pica state
|
|
void Shutdown();
|
|
|
|
extern State g_state; ///< Current Pica state
|
|
|
|
} // namespace
|