mirror of
https://github.com/Lime3DS/Lime3DS
synced 2024-11-16 12:13:44 +00:00
965 lines
25 KiB
C++
965 lines
25 KiB
C++
// Copyright 2006 The Android Open Source Project
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#include <string>
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#include "common/string_util.h"
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#include "core/arm/disassembler/arm_disasm.h"
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static const char *cond_names[] = {
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"eq",
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"ne",
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"cs",
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"cc",
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"mi",
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"pl",
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"vs",
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"vc",
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"hi",
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"ls",
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"ge",
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"lt",
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"gt",
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"le",
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"",
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"RESERVED"
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};
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static const char *opcode_names[] = {
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"invalid",
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"undefined",
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"adc",
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"add",
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"and",
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"b",
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"bl",
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"bic",
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"bkpt",
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"blx",
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"bx",
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"cdp",
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"clz",
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"cmn",
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"cmp",
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"eor",
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"ldc",
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"ldm",
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"ldr",
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"ldrb",
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"ldrbt",
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"ldrh",
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"ldrsb",
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"ldrsh",
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"ldrt",
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"mcr",
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"mla",
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"mov",
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"mrc",
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"mrs",
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"msr",
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"mul",
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"mvn",
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"orr",
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"pld",
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"rsb",
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"rsc",
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"sbc",
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"smlal",
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"smull",
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"stc",
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"stm",
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"str",
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"strb",
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"strbt",
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"strh",
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"strt",
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"sub",
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"swi",
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"swp",
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"swpb",
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"teq",
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"tst",
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"umlal",
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"umull",
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"undefined",
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"adc",
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"add",
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"and",
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"asr",
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"b",
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"bic",
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"bkpt",
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"bl",
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"blx",
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"bx",
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"cmn",
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"cmp",
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"eor",
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"ldmia",
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"ldr",
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"ldrb",
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"ldrh",
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"ldrsb",
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"ldrsh",
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"lsl",
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"lsr",
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"mov",
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"mul",
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"mvn",
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"neg",
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"orr",
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"pop",
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"push",
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"ror",
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"sbc",
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"stmia",
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"str",
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"strb",
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"strh",
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"sub",
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"swi",
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"tst",
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NULL
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};
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// Indexed by the shift type (bits 6-5)
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static const char *shift_names[] = {
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"LSL",
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"LSR",
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"ASR",
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"ROR"
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};
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static const char* cond_to_str(int cond) {
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return cond_names[cond];
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}
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std::string ARM_Disasm::Disassemble(uint32_t addr, uint32_t insn)
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{
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Opcode opcode = Decode(insn);
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switch (opcode) {
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case OP_INVALID:
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return "Invalid";
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case OP_UNDEFINED:
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return "Undefined";
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case OP_ADC:
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case OP_ADD:
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case OP_AND:
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case OP_BIC:
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case OP_CMN:
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case OP_CMP:
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case OP_EOR:
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case OP_MOV:
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case OP_MVN:
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case OP_ORR:
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case OP_RSB:
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case OP_RSC:
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case OP_SBC:
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case OP_SUB:
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case OP_TEQ:
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case OP_TST:
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return DisassembleALU(opcode, insn);
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case OP_B:
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case OP_BL:
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return DisassembleBranch(addr, opcode, insn);
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case OP_BKPT:
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return DisassembleBKPT(insn);
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case OP_BLX:
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// not supported yet
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break;
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case OP_BX:
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return DisassembleBX(insn);
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case OP_CDP:
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return "cdp";
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case OP_CLZ:
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return DisassembleCLZ(insn);
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case OP_LDC:
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return "ldc";
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case OP_LDM:
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case OP_STM:
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return DisassembleMemblock(opcode, insn);
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case OP_LDR:
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case OP_LDRB:
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case OP_LDRBT:
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case OP_LDRT:
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case OP_STR:
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case OP_STRB:
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case OP_STRBT:
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case OP_STRT:
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return DisassembleMem(insn);
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case OP_LDRH:
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case OP_LDRSB:
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case OP_LDRSH:
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case OP_STRH:
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return DisassembleMemHalf(insn);
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case OP_MCR:
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case OP_MRC:
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return DisassembleMCR(opcode, insn);
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case OP_MLA:
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return DisassembleMLA(opcode, insn);
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case OP_MRS:
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return DisassembleMRS(insn);
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case OP_MSR:
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return DisassembleMSR(insn);
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case OP_MUL:
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return DisassembleMUL(opcode, insn);
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case OP_PLD:
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return DisassemblePLD(insn);
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case OP_STC:
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return "stc";
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case OP_SWI:
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return DisassembleSWI(insn);
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case OP_SWP:
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case OP_SWPB:
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return DisassembleSWP(opcode, insn);
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case OP_UMLAL:
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case OP_UMULL:
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case OP_SMLAL:
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case OP_SMULL:
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return DisassembleUMLAL(opcode, insn);
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default:
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return "Error";
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}
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return NULL;
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}
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std::string ARM_Disasm::DisassembleALU(Opcode opcode, uint32_t insn)
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{
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static const uint8_t kNoOperand1 = 1;
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static const uint8_t kNoDest = 2;
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static const uint8_t kNoSbit = 4;
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std::string rn_str;
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std::string rd_str;
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uint8_t flags = 0;
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uint8_t cond = (insn >> 28) & 0xf;
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uint8_t is_immed = (insn >> 25) & 0x1;
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uint8_t bit_s = (insn >> 20) & 1;
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uint8_t rn = (insn >> 16) & 0xf;
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uint8_t rd = (insn >> 12) & 0xf;
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uint8_t immed = insn & 0xff;
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const char* opname = opcode_names[opcode];
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switch (opcode) {
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case OP_CMN:
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case OP_CMP:
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case OP_TEQ:
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case OP_TST:
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flags = kNoDest | kNoSbit;
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break;
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case OP_MOV:
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case OP_MVN:
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flags = kNoOperand1;
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break;
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default:
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break;
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}
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// The "mov" instruction ignores the first operand (rn).
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rn_str[0] = 0;
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if ((flags & kNoOperand1) == 0) {
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rn_str = Common::StringFromFormat("r%d, ", rn);
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}
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// The following instructions do not write the result register (rd):
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// tst, teq, cmp, cmn.
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rd_str[0] = 0;
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if ((flags & kNoDest) == 0) {
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rd_str = Common::StringFromFormat("r%d, ", rd);
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}
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const char *sbit_str = "";
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if (bit_s && !(flags & kNoSbit))
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sbit_str = "s";
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if (is_immed) {
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return Common::StringFromFormat("%s%s%s\t%s%s#%u ; 0x%x",
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opname, cond_to_str(cond), sbit_str, rd_str.c_str(), rn_str.c_str(), immed, immed);
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}
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uint8_t shift_is_reg = (insn >> 4) & 1;
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uint8_t rotate = (insn >> 8) & 0xf;
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uint8_t rm = insn & 0xf;
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uint8_t shift_type = (insn >> 5) & 0x3;
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uint8_t rs = (insn >> 8) & 0xf;
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uint8_t shift_amount = (insn >> 7) & 0x1f;
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uint32_t rotated_val = immed;
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uint8_t rotate2 = rotate << 1;
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rotated_val = (rotated_val >> rotate2) | (rotated_val << (32 - rotate2));
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if (!shift_is_reg && shift_type == 0 && shift_amount == 0) {
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return Common::StringFromFormat("%s%s%s\t%s%sr%d",
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opname, cond_to_str(cond), sbit_str, rd_str.c_str(), rn_str.c_str(), rm);
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}
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const char *shift_name = shift_names[shift_type];
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if (shift_is_reg) {
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return Common::StringFromFormat("%s%s%s\t%s%sr%d, %s r%d",
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opname, cond_to_str(cond), sbit_str, rd_str.c_str(), rn_str.c_str(), rm,
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shift_name, rs);
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}
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if (shift_amount == 0) {
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if (shift_type == 3) {
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return Common::StringFromFormat("%s%s%s\t%s%sr%d, RRX",
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opname, cond_to_str(cond), sbit_str, rd_str.c_str(), rn_str.c_str(), rm);
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}
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shift_amount = 32;
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}
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return Common::StringFromFormat("%s%s%s\t%s%sr%d, %s #%u",
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opname, cond_to_str(cond), sbit_str, rd_str.c_str(), rn_str.c_str(), rm,
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shift_name, shift_amount);
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}
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std::string ARM_Disasm::DisassembleBranch(uint32_t addr, Opcode opcode, uint32_t insn)
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{
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uint8_t cond = (insn >> 28) & 0xf;
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uint32_t offset = insn & 0xffffff;
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// Sign-extend the 24-bit offset
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if ((offset >> 23) & 1)
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offset |= 0xff000000;
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// Pre-compute the left-shift and the prefetch offset
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offset <<= 2;
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offset += 8;
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addr += offset;
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const char *opname = opcode_names[opcode];
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return Common::StringFromFormat("%s%s\t0x%x", opname, cond_to_str(cond), addr);
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}
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std::string ARM_Disasm::DisassembleBX(uint32_t insn)
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{
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uint8_t cond = (insn >> 28) & 0xf;
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uint8_t rn = insn & 0xf;
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return Common::StringFromFormat("bx%s\tr%d", cond_to_str(cond), rn);
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}
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std::string ARM_Disasm::DisassembleBKPT(uint32_t insn)
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{
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uint32_t immed = (((insn >> 8) & 0xfff) << 4) | (insn & 0xf);
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return Common::StringFromFormat("bkpt\t#%d", immed);
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}
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std::string ARM_Disasm::DisassembleCLZ(uint32_t insn)
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{
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uint8_t cond = (insn >> 28) & 0xf;
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uint8_t rd = (insn >> 12) & 0xf;
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uint8_t rm = insn & 0xf;
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return Common::StringFromFormat("clz%s\tr%d, r%d", cond_to_str(cond), rd, rm);
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}
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std::string ARM_Disasm::DisassembleMemblock(Opcode opcode, uint32_t insn)
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{
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std::string tmp_list;
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uint8_t cond = (insn >> 28) & 0xf;
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uint8_t write_back = (insn >> 21) & 0x1;
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uint8_t bit_s = (insn >> 22) & 0x1;
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uint8_t is_up = (insn >> 23) & 0x1;
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uint8_t is_pre = (insn >> 24) & 0x1;
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uint8_t rn = (insn >> 16) & 0xf;
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uint16_t reg_list = insn & 0xffff;
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const char *opname = opcode_names[opcode];
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const char *bang = "";
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if (write_back)
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bang = "!";
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const char *carret = "";
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if (bit_s)
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carret = "^";
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const char *comma = "";
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tmp_list[0] = 0;
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for (int ii = 0; ii < 16; ++ii) {
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if (reg_list & (1 << ii)) {
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tmp_list += Common::StringFromFormat("%sr%d", comma, ii);
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comma = ",";
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}
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}
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const char *addr_mode = "";
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if (is_pre) {
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if (is_up) {
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addr_mode = "ib";
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} else {
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addr_mode = "db";
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}
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} else {
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if (is_up) {
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addr_mode = "ia";
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} else {
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addr_mode = "da";
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}
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}
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return Common::StringFromFormat("%s%s%s\tr%d%s, {%s}%s",
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opname, cond_to_str(cond), addr_mode, rn, bang, tmp_list.c_str(), carret);
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}
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std::string ARM_Disasm::DisassembleMem(uint32_t insn)
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{
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uint8_t cond = (insn >> 28) & 0xf;
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uint8_t is_reg = (insn >> 25) & 0x1;
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uint8_t is_load = (insn >> 20) & 0x1;
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uint8_t write_back = (insn >> 21) & 0x1;
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uint8_t is_byte = (insn >> 22) & 0x1;
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uint8_t is_up = (insn >> 23) & 0x1;
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uint8_t is_pre = (insn >> 24) & 0x1;
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uint8_t rn = (insn >> 16) & 0xf;
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uint8_t rd = (insn >> 12) & 0xf;
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uint16_t offset = insn & 0xfff;
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const char *opname = "ldr";
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if (!is_load)
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opname = "str";
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const char *bang = "";
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if (write_back)
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bang = "!";
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const char *minus = "";
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if (is_up == 0)
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minus = "-";
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const char *byte = "";
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if (is_byte)
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byte = "b";
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if (is_reg == 0) {
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if (is_pre) {
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if (offset == 0) {
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return Common::StringFromFormat("%s%s%s\tr%d, [r%d]",
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opname, cond_to_str(cond), byte, rd, rn);
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} else {
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return Common::StringFromFormat("%s%s%s\tr%d, [r%d, #%s%u]%s",
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opname, cond_to_str(cond), byte, rd, rn, minus, offset, bang);
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}
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} else {
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const char *transfer = "";
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if (write_back)
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transfer = "t";
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return Common::StringFromFormat("%s%s%s%s\tr%d, [r%d], #%s%u",
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opname, cond_to_str(cond), byte, transfer, rd, rn, minus, offset);
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}
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}
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uint8_t rm = insn & 0xf;
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uint8_t shift_type = (insn >> 5) & 0x3;
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uint8_t shift_amount = (insn >> 7) & 0x1f;
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const char *shift_name = shift_names[shift_type];
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if (is_pre) {
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if (shift_amount == 0) {
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if (shift_type == 0) {
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return Common::StringFromFormat("%s%s%s\tr%d, [r%d, %sr%d]%s",
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opname, cond_to_str(cond), byte, rd, rn, minus, rm, bang);
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}
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if (shift_type == 3) {
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return Common::StringFromFormat("%s%s%s\tr%d, [r%d, %sr%d, RRX]%s",
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opname, cond_to_str(cond), byte, rd, rn, minus, rm, bang);
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}
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shift_amount = 32;
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}
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return Common::StringFromFormat("%s%s%s\tr%d, [r%d, %sr%d, %s #%u]%s",
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opname, cond_to_str(cond), byte, rd, rn, minus, rm,
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shift_name, shift_amount, bang);
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}
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const char *transfer = "";
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if (write_back)
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transfer = "t";
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if (shift_amount == 0) {
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if (shift_type == 0) {
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return Common::StringFromFormat("%s%s%s%s\tr%d, [r%d], %sr%d",
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opname, cond_to_str(cond), byte, transfer, rd, rn, minus, rm);
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}
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if (shift_type == 3) {
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return Common::StringFromFormat("%s%s%s%s\tr%d, [r%d], %sr%d, RRX",
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opname, cond_to_str(cond), byte, transfer, rd, rn, minus, rm);
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}
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shift_amount = 32;
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}
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return Common::StringFromFormat("%s%s%s%s\tr%d, [r%d], %sr%d, %s #%u",
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opname, cond_to_str(cond), byte, transfer, rd, rn, minus, rm,
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shift_name, shift_amount);
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}
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std::string ARM_Disasm::DisassembleMemHalf(uint32_t insn)
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{
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uint8_t cond = (insn >> 28) & 0xf;
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uint8_t is_load = (insn >> 20) & 0x1;
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uint8_t write_back = (insn >> 21) & 0x1;
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uint8_t is_immed = (insn >> 22) & 0x1;
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uint8_t is_up = (insn >> 23) & 0x1;
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uint8_t is_pre = (insn >> 24) & 0x1;
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uint8_t rn = (insn >> 16) & 0xf;
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uint8_t rd = (insn >> 12) & 0xf;
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uint8_t bits_65 = (insn >> 5) & 0x3;
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uint8_t rm = insn & 0xf;
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uint8_t offset = (((insn >> 8) & 0xf) << 4) | (insn & 0xf);
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const char *opname = "ldr";
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if (is_load == 0)
|
|
opname = "str";
|
|
|
|
const char *width = "";
|
|
if (bits_65 == 1)
|
|
width = "h";
|
|
else if (bits_65 == 2)
|
|
width = "sb";
|
|
else
|
|
width = "sh";
|
|
|
|
const char *bang = "";
|
|
if (write_back)
|
|
bang = "!";
|
|
const char *minus = "";
|
|
if (is_up == 0)
|
|
minus = "-";
|
|
|
|
if (is_immed) {
|
|
if (is_pre) {
|
|
if (offset == 0) {
|
|
return Common::StringFromFormat("%s%sh\tr%d, [r%d]", opname, cond_to_str(cond), rd, rn);
|
|
} else {
|
|
return Common::StringFromFormat("%s%sh\tr%d, [r%d, #%s%u]%s",
|
|
opname, cond_to_str(cond), rd, rn, minus, offset, bang);
|
|
}
|
|
} else {
|
|
return Common::StringFromFormat("%s%sh\tr%d, [r%d], #%s%u",
|
|
opname, cond_to_str(cond), rd, rn, minus, offset);
|
|
}
|
|
}
|
|
|
|
if (is_pre) {
|
|
return Common::StringFromFormat("%s%sh\tr%d, [r%d, %sr%d]%s",
|
|
opname, cond_to_str(cond), rd, rn, minus, rm, bang);
|
|
} else {
|
|
return Common::StringFromFormat("%s%sh\tr%d, [r%d], %sr%d",
|
|
opname, cond_to_str(cond), rd, rn, minus, rm);
|
|
}
|
|
}
|
|
|
|
std::string ARM_Disasm::DisassembleMCR(Opcode opcode, uint32_t insn)
|
|
{
|
|
uint8_t cond = (insn >> 28) & 0xf;
|
|
uint8_t crn = (insn >> 16) & 0xf;
|
|
uint8_t crd = (insn >> 12) & 0xf;
|
|
uint8_t cpnum = (insn >> 8) & 0xf;
|
|
uint8_t opcode2 = (insn >> 5) & 0x7;
|
|
uint8_t crm = insn & 0xf;
|
|
|
|
const char *opname = opcode_names[opcode];
|
|
return Common::StringFromFormat("%s%s\t%d, 0, r%d, cr%d, cr%d, {%d}",
|
|
opname, cond_to_str(cond), cpnum, crd, crn, crm, opcode2);
|
|
}
|
|
|
|
std::string ARM_Disasm::DisassembleMLA(Opcode opcode, uint32_t insn)
|
|
{
|
|
uint8_t cond = (insn >> 28) & 0xf;
|
|
uint8_t rd = (insn >> 16) & 0xf;
|
|
uint8_t rn = (insn >> 12) & 0xf;
|
|
uint8_t rs = (insn >> 8) & 0xf;
|
|
uint8_t rm = insn & 0xf;
|
|
uint8_t bit_s = (insn >> 20) & 1;
|
|
|
|
const char *opname = opcode_names[opcode];
|
|
return Common::StringFromFormat("%s%s%s\tr%d, r%d, r%d, r%d",
|
|
opname, cond_to_str(cond), bit_s ? "s" : "", rd, rm, rs, rn);
|
|
}
|
|
|
|
std::string ARM_Disasm::DisassembleUMLAL(Opcode opcode, uint32_t insn)
|
|
{
|
|
uint8_t cond = (insn >> 28) & 0xf;
|
|
uint8_t rdhi = (insn >> 16) & 0xf;
|
|
uint8_t rdlo = (insn >> 12) & 0xf;
|
|
uint8_t rs = (insn >> 8) & 0xf;
|
|
uint8_t rm = insn & 0xf;
|
|
uint8_t bit_s = (insn >> 20) & 1;
|
|
|
|
const char *opname = opcode_names[opcode];
|
|
return Common::StringFromFormat("%s%s%s\tr%d, r%d, r%d, r%d",
|
|
opname, cond_to_str(cond), bit_s ? "s" : "", rdlo, rdhi, rm, rs);
|
|
}
|
|
|
|
std::string ARM_Disasm::DisassembleMUL(Opcode opcode, uint32_t insn)
|
|
{
|
|
uint8_t cond = (insn >> 28) & 0xf;
|
|
uint8_t rd = (insn >> 16) & 0xf;
|
|
uint8_t rs = (insn >> 8) & 0xf;
|
|
uint8_t rm = insn & 0xf;
|
|
uint8_t bit_s = (insn >> 20) & 1;
|
|
|
|
const char *opname = opcode_names[opcode];
|
|
return Common::StringFromFormat("%s%s%s\tr%d, r%d, r%d",
|
|
opname, cond_to_str(cond), bit_s ? "s" : "", rd, rm, rs);
|
|
}
|
|
|
|
std::string ARM_Disasm::DisassembleMRS(uint32_t insn)
|
|
{
|
|
uint8_t cond = (insn >> 28) & 0xf;
|
|
uint8_t rd = (insn >> 12) & 0xf;
|
|
uint8_t ps = (insn >> 22) & 1;
|
|
|
|
return Common::StringFromFormat("mrs%s\tr%d, %s", cond_to_str(cond), rd, ps ? "spsr" : "cpsr");
|
|
}
|
|
|
|
std::string ARM_Disasm::DisassembleMSR(uint32_t insn)
|
|
{
|
|
char flags[8];
|
|
int flag_index = 0;
|
|
uint8_t cond = (insn >> 28) & 0xf;
|
|
uint8_t is_immed = (insn >> 25) & 0x1;
|
|
uint8_t pd = (insn >> 22) & 1;
|
|
uint8_t mask = (insn >> 16) & 0xf;
|
|
|
|
if (mask & 1)
|
|
flags[flag_index++] = 'c';
|
|
if (mask & 2)
|
|
flags[flag_index++] = 'x';
|
|
if (mask & 4)
|
|
flags[flag_index++] = 's';
|
|
if (mask & 8)
|
|
flags[flag_index++] = 'f';
|
|
flags[flag_index] = 0;
|
|
|
|
if (is_immed) {
|
|
uint32_t immed = insn & 0xff;
|
|
uint8_t rotate = (insn >> 8) & 0xf;
|
|
uint8_t rotate2 = rotate << 1;
|
|
uint32_t rotated_val = (immed >> rotate2) | (immed << (32 - rotate2));
|
|
return Common::StringFromFormat("msr%s\t%s_%s, #0x%x",
|
|
cond_to_str(cond), pd ? "spsr" : "cpsr", flags, rotated_val);
|
|
}
|
|
|
|
uint8_t rm = insn & 0xf;
|
|
|
|
return Common::StringFromFormat("msr%s\t%s_%s, r%d",
|
|
cond_to_str(cond), pd ? "spsr" : "cpsr", flags, rm);
|
|
}
|
|
|
|
std::string ARM_Disasm::DisassemblePLD(uint32_t insn)
|
|
{
|
|
uint8_t is_reg = (insn >> 25) & 0x1;
|
|
uint8_t is_up = (insn >> 23) & 0x1;
|
|
uint8_t rn = (insn >> 16) & 0xf;
|
|
|
|
const char *minus = "";
|
|
if (is_up == 0)
|
|
minus = "-";
|
|
|
|
if (is_reg) {
|
|
uint8_t rm = insn & 0xf;
|
|
return Common::StringFromFormat("pld\t[r%d, %sr%d]", rn, minus, rm);
|
|
}
|
|
|
|
uint16_t offset = insn & 0xfff;
|
|
if (offset == 0) {
|
|
return Common::StringFromFormat("pld\t[r%d]", rn);
|
|
} else {
|
|
return Common::StringFromFormat("pld\t[r%d, #%s%u]", rn, minus, offset);
|
|
}
|
|
}
|
|
|
|
std::string ARM_Disasm::DisassembleSWI(uint32_t insn)
|
|
{
|
|
uint8_t cond = (insn >> 28) & 0xf;
|
|
uint32_t sysnum = insn & 0x00ffffff;
|
|
|
|
return Common::StringFromFormat("swi%s 0x%x", cond_to_str(cond), sysnum);
|
|
}
|
|
|
|
std::string ARM_Disasm::DisassembleSWP(Opcode opcode, uint32_t insn)
|
|
{
|
|
uint8_t cond = (insn >> 28) & 0xf;
|
|
uint8_t rn = (insn >> 16) & 0xf;
|
|
uint8_t rd = (insn >> 12) & 0xf;
|
|
uint8_t rm = insn & 0xf;
|
|
|
|
const char *opname = opcode_names[opcode];
|
|
return Common::StringFromFormat("%s%s\tr%d, r%d, [r%d]", opname, cond_to_str(cond), rd, rm, rn);
|
|
}
|
|
|
|
Opcode ARM_Disasm::Decode(uint32_t insn) {
|
|
uint32_t bits27_26 = (insn >> 26) & 0x3;
|
|
switch (bits27_26) {
|
|
case 0x0:
|
|
return Decode00(insn);
|
|
case 0x1:
|
|
return Decode01(insn);
|
|
case 0x2:
|
|
return Decode10(insn);
|
|
case 0x3:
|
|
return Decode11(insn);
|
|
}
|
|
return OP_INVALID;
|
|
}
|
|
|
|
Opcode ARM_Disasm::Decode00(uint32_t insn) {
|
|
uint8_t bit25 = (insn >> 25) & 0x1;
|
|
uint8_t bit4 = (insn >> 4) & 0x1;
|
|
if (bit25 == 0 && bit4 == 1) {
|
|
if ((insn & 0x0ffffff0) == 0x012fff10) {
|
|
// Bx instruction
|
|
return OP_BX;
|
|
}
|
|
if ((insn & 0x0ff000f0) == 0x01600010) {
|
|
// Clz instruction
|
|
return OP_CLZ;
|
|
}
|
|
if ((insn & 0xfff000f0) == 0xe1200070) {
|
|
// Bkpt instruction
|
|
return OP_BKPT;
|
|
}
|
|
uint32_t bits7_4 = (insn >> 4) & 0xf;
|
|
if (bits7_4 == 0x9) {
|
|
if ((insn & 0x0ff00ff0) == 0x01000090) {
|
|
// Swp instruction
|
|
uint8_t bit22 = (insn >> 22) & 0x1;
|
|
if (bit22)
|
|
return OP_SWPB;
|
|
return OP_SWP;
|
|
}
|
|
// One of the multiply instructions
|
|
return DecodeMUL(insn);
|
|
}
|
|
|
|
uint8_t bit7 = (insn >> 7) & 0x1;
|
|
if (bit7 == 1) {
|
|
// One of the load/store halfword/byte instructions
|
|
return DecodeLDRH(insn);
|
|
}
|
|
}
|
|
|
|
// One of the data processing instructions
|
|
return DecodeALU(insn);
|
|
}
|
|
|
|
Opcode ARM_Disasm::Decode01(uint32_t insn) {
|
|
uint8_t is_reg = (insn >> 25) & 0x1;
|
|
uint8_t bit4 = (insn >> 4) & 0x1;
|
|
if (is_reg == 1 && bit4 == 1)
|
|
return OP_UNDEFINED;
|
|
uint8_t is_load = (insn >> 20) & 0x1;
|
|
uint8_t is_byte = (insn >> 22) & 0x1;
|
|
if ((insn & 0xfd70f000) == 0xf550f000) {
|
|
// Pre-load
|
|
return OP_PLD;
|
|
}
|
|
if (is_load) {
|
|
if (is_byte) {
|
|
// Load byte
|
|
return OP_LDRB;
|
|
}
|
|
// Load word
|
|
return OP_LDR;
|
|
}
|
|
if (is_byte) {
|
|
// Store byte
|
|
return OP_STRB;
|
|
}
|
|
// Store word
|
|
return OP_STR;
|
|
}
|
|
|
|
Opcode ARM_Disasm::Decode10(uint32_t insn) {
|
|
uint8_t bit25 = (insn >> 25) & 0x1;
|
|
if (bit25 == 0) {
|
|
// LDM/STM
|
|
uint8_t is_load = (insn >> 20) & 0x1;
|
|
if (is_load)
|
|
return OP_LDM;
|
|
return OP_STM;
|
|
}
|
|
// Branch or Branch with link
|
|
uint8_t is_link = (insn >> 24) & 1;
|
|
uint32_t offset = insn & 0xffffff;
|
|
|
|
// Sign-extend the 24-bit offset
|
|
if ((offset >> 23) & 1)
|
|
offset |= 0xff000000;
|
|
|
|
// Pre-compute the left-shift and the prefetch offset
|
|
offset <<= 2;
|
|
offset += 8;
|
|
if (is_link == 0)
|
|
return OP_B;
|
|
return OP_BL;
|
|
}
|
|
|
|
Opcode ARM_Disasm::Decode11(uint32_t insn) {
|
|
uint8_t bit25 = (insn >> 25) & 0x1;
|
|
if (bit25 == 0) {
|
|
// LDC, SDC
|
|
uint8_t is_load = (insn >> 20) & 0x1;
|
|
if (is_load) {
|
|
// LDC
|
|
return OP_LDC;
|
|
}
|
|
// STC
|
|
return OP_STC;
|
|
}
|
|
|
|
uint8_t bit24 = (insn >> 24) & 0x1;
|
|
if (bit24 == 0x1) {
|
|
// SWI
|
|
return OP_SWI;
|
|
}
|
|
|
|
uint8_t bit4 = (insn >> 4) & 0x1;
|
|
uint8_t cpnum = (insn >> 8) & 0xf;
|
|
|
|
if (cpnum == 15) {
|
|
// Special case for coprocessor 15
|
|
uint8_t opcode = (insn >> 21) & 0x7;
|
|
if (bit4 == 0 || opcode != 0) {
|
|
// This is an unexpected bit pattern. Create an undefined
|
|
// instruction in case this is ever executed.
|
|
return OP_UNDEFINED;
|
|
}
|
|
|
|
// MRC, MCR
|
|
uint8_t is_mrc = (insn >> 20) & 0x1;
|
|
if (is_mrc)
|
|
return OP_MRC;
|
|
return OP_MCR;
|
|
}
|
|
|
|
if (bit4 == 0) {
|
|
// CDP
|
|
return OP_CDP;
|
|
}
|
|
// MRC, MCR
|
|
uint8_t is_mrc = (insn >> 20) & 0x1;
|
|
if (is_mrc)
|
|
return OP_MRC;
|
|
return OP_MCR;
|
|
}
|
|
|
|
Opcode ARM_Disasm::DecodeMUL(uint32_t insn) {
|
|
uint8_t bit24 = (insn >> 24) & 0x1;
|
|
if (bit24 != 0) {
|
|
// This is an unexpected bit pattern. Create an undefined
|
|
// instruction in case this is ever executed.
|
|
return OP_UNDEFINED;
|
|
}
|
|
uint8_t bit23 = (insn >> 23) & 0x1;
|
|
uint8_t bit22_U = (insn >> 22) & 0x1;
|
|
uint8_t bit21_A = (insn >> 21) & 0x1;
|
|
if (bit23 == 0) {
|
|
// 32-bit multiply
|
|
if (bit22_U != 0) {
|
|
// This is an unexpected bit pattern. Create an undefined
|
|
// instruction in case this is ever executed.
|
|
return OP_UNDEFINED;
|
|
}
|
|
if (bit21_A == 0)
|
|
return OP_MUL;
|
|
return OP_MLA;
|
|
}
|
|
// 64-bit multiply
|
|
if (bit22_U == 0) {
|
|
// Unsigned multiply long
|
|
if (bit21_A == 0)
|
|
return OP_UMULL;
|
|
return OP_UMLAL;
|
|
}
|
|
// Signed multiply long
|
|
if (bit21_A == 0)
|
|
return OP_SMULL;
|
|
return OP_SMLAL;
|
|
}
|
|
|
|
Opcode ARM_Disasm::DecodeLDRH(uint32_t insn) {
|
|
uint8_t is_load = (insn >> 20) & 0x1;
|
|
uint8_t bits_65 = (insn >> 5) & 0x3;
|
|
if (is_load) {
|
|
if (bits_65 == 0x1) {
|
|
// Load unsigned halfword
|
|
return OP_LDRH;
|
|
} else if (bits_65 == 0x2) {
|
|
// Load signed byte
|
|
return OP_LDRSB;
|
|
}
|
|
// Signed halfword
|
|
if (bits_65 != 0x3) {
|
|
// This is an unexpected bit pattern. Create an undefined
|
|
// instruction in case this is ever executed.
|
|
return OP_UNDEFINED;
|
|
}
|
|
// Load signed halfword
|
|
return OP_LDRSH;
|
|
}
|
|
// Store halfword
|
|
if (bits_65 != 0x1) {
|
|
// This is an unexpected bit pattern. Create an undefined
|
|
// instruction in case this is ever executed.
|
|
return OP_UNDEFINED;
|
|
}
|
|
// Store halfword
|
|
return OP_STRH;
|
|
}
|
|
|
|
Opcode ARM_Disasm::DecodeALU(uint32_t insn) {
|
|
uint8_t is_immed = (insn >> 25) & 0x1;
|
|
uint8_t opcode = (insn >> 21) & 0xf;
|
|
uint8_t bit_s = (insn >> 20) & 1;
|
|
uint8_t shift_is_reg = (insn >> 4) & 1;
|
|
uint8_t bit7 = (insn >> 7) & 1;
|
|
if (!is_immed && shift_is_reg && (bit7 != 0)) {
|
|
// This is an unexpected bit pattern. Create an undefined
|
|
// instruction in case this is ever executed.
|
|
return OP_UNDEFINED;
|
|
}
|
|
switch (opcode) {
|
|
case 0x0:
|
|
return OP_AND;
|
|
case 0x1:
|
|
return OP_EOR;
|
|
case 0x2:
|
|
return OP_SUB;
|
|
case 0x3:
|
|
return OP_RSB;
|
|
case 0x4:
|
|
return OP_ADD;
|
|
case 0x5:
|
|
return OP_ADC;
|
|
case 0x6:
|
|
return OP_SBC;
|
|
case 0x7:
|
|
return OP_RSC;
|
|
case 0x8:
|
|
if (bit_s)
|
|
return OP_TST;
|
|
return OP_MRS;
|
|
case 0x9:
|
|
if (bit_s)
|
|
return OP_TEQ;
|
|
return OP_MSR;
|
|
case 0xa:
|
|
if (bit_s)
|
|
return OP_CMP;
|
|
return OP_MRS;
|
|
case 0xb:
|
|
if (bit_s)
|
|
return OP_CMN;
|
|
return OP_MSR;
|
|
case 0xc:
|
|
return OP_ORR;
|
|
case 0xd:
|
|
return OP_MOV;
|
|
case 0xe:
|
|
return OP_BIC;
|
|
case 0xf:
|
|
return OP_MVN;
|
|
}
|
|
// Unreachable
|
|
return OP_INVALID;
|
|
}
|