2021-05-21 03:38:38 +00:00
|
|
|
// Copyright 2021 yuzu Emulator Project
|
|
|
|
// Licensed under GPLv2 or any later version
|
|
|
|
// Refer to the license.txt file included.
|
|
|
|
|
|
|
|
#include <string_view>
|
|
|
|
|
|
|
|
#include "shader_recompiler/backend/glsl/emit_context.h"
|
2021-05-29 06:09:29 +00:00
|
|
|
#include "shader_recompiler/backend/glsl/emit_glsl_instructions.h"
|
2021-05-21 03:38:38 +00:00
|
|
|
#include "shader_recompiler/frontend/ir/value.h"
|
|
|
|
|
|
|
|
namespace Shader::Backend::GLSL {
|
2021-05-29 01:24:52 +00:00
|
|
|
void EmitLoadStorageU8([[maybe_unused]] EmitContext& ctx, IR::Inst& inst,
|
|
|
|
[[maybe_unused]] const IR::Value& binding,
|
2021-05-21 03:38:38 +00:00
|
|
|
[[maybe_unused]] const IR::Value& offset) {
|
2021-05-29 01:24:52 +00:00
|
|
|
const auto offset_var{ctx.reg_alloc.Consume(offset)};
|
|
|
|
ctx.AddU32("{}=bitfieldExtract(ssbo{}[{}/4],int({}%4)*8,8);", inst, binding.U32(), offset_var,
|
|
|
|
offset_var);
|
2021-05-21 03:38:38 +00:00
|
|
|
}
|
|
|
|
|
2021-05-29 01:24:52 +00:00
|
|
|
void EmitLoadStorageS8([[maybe_unused]] EmitContext& ctx, IR::Inst& inst,
|
|
|
|
[[maybe_unused]] const IR::Value& binding,
|
2021-05-21 03:38:38 +00:00
|
|
|
[[maybe_unused]] const IR::Value& offset) {
|
2021-05-29 01:24:52 +00:00
|
|
|
const auto offset_var{ctx.reg_alloc.Consume(offset)};
|
|
|
|
ctx.AddS32("{}=bitfieldExtract(int(ssbo{}[{}/4]),int({}%4)*8,8);", inst, binding.U32(),
|
|
|
|
offset_var, offset_var);
|
2021-05-21 03:38:38 +00:00
|
|
|
}
|
|
|
|
|
2021-05-29 01:24:52 +00:00
|
|
|
void EmitLoadStorageU16([[maybe_unused]] EmitContext& ctx, IR::Inst& inst,
|
2021-05-21 03:38:38 +00:00
|
|
|
[[maybe_unused]] const IR::Value& binding,
|
|
|
|
[[maybe_unused]] const IR::Value& offset) {
|
2021-05-29 01:24:52 +00:00
|
|
|
const auto offset_var{ctx.reg_alloc.Consume(offset)};
|
|
|
|
ctx.AddU32("{}=bitfieldExtract(ssbo{}[{}/4],int(({}/2)%2)*16,16);", inst, binding.U32(),
|
|
|
|
offset_var, offset_var);
|
2021-05-21 03:38:38 +00:00
|
|
|
}
|
|
|
|
|
2021-05-29 01:24:52 +00:00
|
|
|
void EmitLoadStorageS16([[maybe_unused]] EmitContext& ctx, IR::Inst& inst,
|
2021-05-21 03:38:38 +00:00
|
|
|
[[maybe_unused]] const IR::Value& binding,
|
|
|
|
[[maybe_unused]] const IR::Value& offset) {
|
2021-05-29 01:24:52 +00:00
|
|
|
const auto offset_var{ctx.reg_alloc.Consume(offset)};
|
|
|
|
ctx.AddS32("{}=bitfieldExtract(int(ssbo{}[{}/4]),int(({}/2)%2)*16,16);", inst, binding.U32(),
|
|
|
|
offset_var, offset_var);
|
2021-05-21 03:38:38 +00:00
|
|
|
}
|
|
|
|
|
2021-05-24 22:35:37 +00:00
|
|
|
void EmitLoadStorage32(EmitContext& ctx, IR::Inst& inst, const IR::Value& binding,
|
|
|
|
const IR::Value& offset) {
|
2021-05-27 04:26:16 +00:00
|
|
|
const auto offset_var{ctx.reg_alloc.Consume(offset)};
|
2021-05-29 01:24:52 +00:00
|
|
|
ctx.AddU32("{}=ssbo{}[{}/4];", inst, binding.U32(), offset_var);
|
2021-05-21 03:38:38 +00:00
|
|
|
}
|
|
|
|
|
2021-05-25 05:35:30 +00:00
|
|
|
void EmitLoadStorage64(EmitContext& ctx, IR::Inst& inst, const IR::Value& binding,
|
|
|
|
const IR::Value& offset) {
|
2021-05-27 04:26:16 +00:00
|
|
|
const auto offset_var{ctx.reg_alloc.Consume(offset)};
|
2021-05-29 01:24:52 +00:00
|
|
|
ctx.AddU32x2("{}=uvec2(ssbo{}[{}/4],ssbo{}[{}/4+1]);", inst, binding.U32(), offset_var,
|
2021-05-27 04:26:16 +00:00
|
|
|
binding.U32(), offset_var);
|
2021-05-21 03:38:38 +00:00
|
|
|
}
|
|
|
|
|
2021-05-27 04:26:16 +00:00
|
|
|
void EmitLoadStorage128(EmitContext& ctx, IR::Inst& inst, const IR::Value& binding,
|
|
|
|
const IR::Value& offset) {
|
|
|
|
const auto offset_var{ctx.reg_alloc.Consume(offset)};
|
2021-05-29 01:24:52 +00:00
|
|
|
ctx.AddU32x4("{}=uvec4(ssbo{}[{}/4],ssbo{}[{}/4+1],ssbo{}[{}/4+2],ssbo{}[{}/4+3]);", inst,
|
2021-05-27 04:26:16 +00:00
|
|
|
binding.U32(), offset_var, binding.U32(), offset_var, binding.U32(), offset_var,
|
|
|
|
binding.U32(), offset_var);
|
2021-05-21 03:38:38 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
void EmitWriteStorageU8([[maybe_unused]] EmitContext& ctx,
|
|
|
|
[[maybe_unused]] const IR::Value& binding,
|
|
|
|
[[maybe_unused]] const IR::Value& offset,
|
2021-05-21 23:55:58 +00:00
|
|
|
[[maybe_unused]] std::string_view value) {
|
2021-05-29 01:24:52 +00:00
|
|
|
const auto offset_var{ctx.reg_alloc.Consume(offset)};
|
|
|
|
ctx.Add("ssbo{}[{}/4]=bitfieldInsert(ssbo{}[{}/4],{},int({}%4)*8,8);", binding.U32(),
|
|
|
|
offset_var, binding.U32(), offset_var, value, offset_var);
|
2021-05-21 03:38:38 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
void EmitWriteStorageS8([[maybe_unused]] EmitContext& ctx,
|
|
|
|
[[maybe_unused]] const IR::Value& binding,
|
|
|
|
[[maybe_unused]] const IR::Value& offset,
|
2021-05-21 23:55:58 +00:00
|
|
|
[[maybe_unused]] std::string_view value) {
|
2021-05-29 01:24:52 +00:00
|
|
|
const auto offset_var{ctx.reg_alloc.Consume(offset)};
|
|
|
|
ctx.Add("ssbo{}[{}/4]=bitfieldInsert(ssbo{}[{}/4],{},int({}%4)*8,8);", binding.U32(),
|
|
|
|
offset_var, binding.U32(), offset_var, value, offset_var);
|
2021-05-21 03:38:38 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
void EmitWriteStorageU16([[maybe_unused]] EmitContext& ctx,
|
|
|
|
[[maybe_unused]] const IR::Value& binding,
|
|
|
|
[[maybe_unused]] const IR::Value& offset,
|
2021-05-21 23:55:58 +00:00
|
|
|
[[maybe_unused]] std::string_view value) {
|
2021-05-29 01:24:52 +00:00
|
|
|
const auto offset_var{ctx.reg_alloc.Consume(offset)};
|
|
|
|
ctx.Add("ssbo{}[{}/4]=bitfieldInsert(ssbo{}[{}/4],{},int(({}/2)%2)*16,16);", binding.U32(),
|
|
|
|
offset_var, binding.U32(), offset_var, value, offset_var);
|
2021-05-21 03:38:38 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
void EmitWriteStorageS16([[maybe_unused]] EmitContext& ctx,
|
|
|
|
[[maybe_unused]] const IR::Value& binding,
|
|
|
|
[[maybe_unused]] const IR::Value& offset,
|
2021-05-21 23:55:58 +00:00
|
|
|
[[maybe_unused]] std::string_view value) {
|
2021-05-29 01:24:52 +00:00
|
|
|
const auto offset_var{ctx.reg_alloc.Consume(offset)};
|
|
|
|
ctx.Add("ssbo{}[{}/4]=bitfieldInsert(ssbo{}[{}/4],{},int(({}/2)%2)*16,16);", binding.U32(),
|
|
|
|
offset_var, binding.U32(), offset_var, value, offset_var);
|
2021-05-21 03:38:38 +00:00
|
|
|
}
|
|
|
|
|
2021-05-22 05:52:03 +00:00
|
|
|
void EmitWriteStorage32(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset,
|
|
|
|
std::string_view value) {
|
2021-05-28 17:55:07 +00:00
|
|
|
const auto offset_var{ctx.reg_alloc.Consume(offset)};
|
2021-05-29 01:24:52 +00:00
|
|
|
ctx.Add("ssbo{}[{}/4]={};", binding.U32(), offset_var, value);
|
2021-05-21 03:38:38 +00:00
|
|
|
}
|
|
|
|
|
2021-05-22 05:52:03 +00:00
|
|
|
void EmitWriteStorage64(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset,
|
|
|
|
std::string_view value) {
|
2021-05-28 17:55:07 +00:00
|
|
|
const auto offset_var{ctx.reg_alloc.Consume(offset)};
|
2021-05-29 01:24:52 +00:00
|
|
|
ctx.Add("ssbo{}[{}/4]={}.x;", binding.U32(), offset_var, value);
|
|
|
|
ctx.Add("ssbo{}[({}/4)+1]={}.y;", binding.U32(), offset_var, value);
|
2021-05-21 03:38:38 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
void EmitWriteStorage128([[maybe_unused]] EmitContext& ctx,
|
|
|
|
[[maybe_unused]] const IR::Value& binding,
|
|
|
|
[[maybe_unused]] const IR::Value& offset,
|
2021-05-21 23:55:58 +00:00
|
|
|
[[maybe_unused]] std::string_view value) {
|
2021-05-29 01:24:52 +00:00
|
|
|
const auto offset_var{ctx.reg_alloc.Consume(offset)};
|
|
|
|
ctx.Add("ssbo{}[{}/4]={}.x;", binding.U32(), offset_var, value);
|
|
|
|
ctx.Add("ssbo{}[({}/4)+1]={}.y;", binding.U32(), offset_var, value);
|
|
|
|
ctx.Add("ssbo{}[({}/4)+2]={}.z;", binding.U32(), offset_var, value);
|
|
|
|
ctx.Add("ssbo{}[({}/4)+3]={}.w;", binding.U32(), offset_var, value);
|
2021-05-21 03:38:38 +00:00
|
|
|
}
|
|
|
|
} // namespace Shader::Backend::GLSL
|