2022-04-28 11:24:11 -05:00
|
|
|
// SPDX-FileCopyrightText: Ryujinx Team and Contributors
|
|
|
|
// SPDX-License-Identifier: MIT
|
2020-10-26 22:07:36 -05:00
|
|
|
|
2021-01-15 01:02:57 -06:00
|
|
|
#include <bit>
|
2020-10-26 22:07:36 -05:00
|
|
|
#include "video_core/cdma_pusher.h"
|
|
|
|
#include "video_core/engines/maxwell_3d.h"
|
|
|
|
#include "video_core/gpu.h"
|
2022-01-30 03:31:13 -06:00
|
|
|
#include "video_core/host1x/control.h"
|
|
|
|
#include "video_core/host1x/nvdec.h"
|
|
|
|
#include "video_core/host1x/nvdec_common.h"
|
|
|
|
#include "video_core/host1x/sync_manager.h"
|
|
|
|
#include "video_core/host1x/vic.h"
|
|
|
|
#include "video_core/memory_manager.h"
|
2020-10-26 22:07:36 -05:00
|
|
|
|
|
|
|
namespace Tegra {
|
2020-12-04 13:39:12 -06:00
|
|
|
CDmaPusher::CDmaPusher(GPU& gpu_)
|
2022-01-30 03:31:13 -06:00
|
|
|
: gpu{gpu_}, nvdec_processor(std::make_shared<Host1x::Nvdec>(gpu)),
|
|
|
|
vic_processor(std::make_unique<Host1x::Vic>(gpu, nvdec_processor)),
|
|
|
|
host1x_processor(std::make_unique<Host1x::Control>(gpu)),
|
|
|
|
sync_manager(std::make_unique<Host1x::SyncptIncrManager>(gpu)) {}
|
2020-10-26 22:07:36 -05:00
|
|
|
|
|
|
|
CDmaPusher::~CDmaPusher() = default;
|
|
|
|
|
2020-11-23 12:25:01 -06:00
|
|
|
void CDmaPusher::ProcessEntries(ChCommandHeaderList&& entries) {
|
2020-11-23 14:01:40 -06:00
|
|
|
for (const auto& value : entries) {
|
2020-10-26 22:07:36 -05:00
|
|
|
if (mask != 0) {
|
2021-01-15 01:02:57 -06:00
|
|
|
const auto lbs = static_cast<u32>(std::countr_zero(mask));
|
2020-10-26 22:07:36 -05:00
|
|
|
mask &= ~(1U << lbs);
|
2020-11-23 14:01:40 -06:00
|
|
|
ExecuteCommand(offset + lbs, value.raw);
|
2020-10-26 22:07:36 -05:00
|
|
|
continue;
|
|
|
|
} else if (count != 0) {
|
|
|
|
--count;
|
2020-11-23 14:01:40 -06:00
|
|
|
ExecuteCommand(offset, value.raw);
|
2020-10-26 22:07:36 -05:00
|
|
|
if (incrementing) {
|
|
|
|
++offset;
|
|
|
|
}
|
|
|
|
continue;
|
|
|
|
}
|
2020-11-23 14:01:40 -06:00
|
|
|
const auto mode = value.submission_mode.Value();
|
2020-10-26 22:07:36 -05:00
|
|
|
switch (mode) {
|
|
|
|
case ChSubmissionMode::SetClass: {
|
2020-11-23 14:01:40 -06:00
|
|
|
mask = value.value & 0x3f;
|
|
|
|
offset = value.method_offset;
|
|
|
|
current_class = static_cast<ChClassId>((value.value >> 6) & 0x3ff);
|
2020-10-26 22:07:36 -05:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
case ChSubmissionMode::Incrementing:
|
|
|
|
case ChSubmissionMode::NonIncrementing:
|
2020-11-23 14:01:40 -06:00
|
|
|
count = value.value;
|
|
|
|
offset = value.method_offset;
|
2020-10-26 22:07:36 -05:00
|
|
|
incrementing = mode == ChSubmissionMode::Incrementing;
|
|
|
|
break;
|
|
|
|
case ChSubmissionMode::Mask:
|
2020-11-23 14:01:40 -06:00
|
|
|
mask = value.value;
|
|
|
|
offset = value.method_offset;
|
2020-10-26 22:07:36 -05:00
|
|
|
break;
|
|
|
|
case ChSubmissionMode::Immediate: {
|
2020-11-23 14:01:40 -06:00
|
|
|
const u32 data = value.value & 0xfff;
|
|
|
|
offset = value.method_offset;
|
|
|
|
ExecuteCommand(offset, data);
|
2020-10-26 22:07:36 -05:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
default:
|
|
|
|
UNIMPLEMENTED_MSG("ChSubmission mode {} is not implemented!", static_cast<u32>(mode));
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2020-12-04 13:39:12 -06:00
|
|
|
void CDmaPusher::ExecuteCommand(u32 state_offset, u32 data) {
|
2020-10-26 22:07:36 -05:00
|
|
|
switch (current_class) {
|
|
|
|
case ChClassId::NvDec:
|
2020-11-23 14:01:40 -06:00
|
|
|
ThiStateWrite(nvdec_thi_state, offset, data);
|
|
|
|
switch (static_cast<ThiMethod>(offset)) {
|
2020-10-26 22:07:36 -05:00
|
|
|
case ThiMethod::IncSyncpt: {
|
|
|
|
LOG_DEBUG(Service_NVDRV, "NVDEC Class IncSyncpt Method");
|
|
|
|
const auto syncpoint_id = static_cast<u32>(data & 0xFF);
|
|
|
|
const auto cond = static_cast<u32>((data >> 8) & 0xFF);
|
|
|
|
if (cond == 0) {
|
2020-12-28 00:02:06 -06:00
|
|
|
sync_manager->Increment(syncpoint_id);
|
2020-10-26 22:07:36 -05:00
|
|
|
} else {
|
2020-12-28 00:02:06 -06:00
|
|
|
sync_manager->SignalDone(
|
|
|
|
sync_manager->IncrementWhenDone(static_cast<u32>(current_class), syncpoint_id));
|
2020-10-26 22:07:36 -05:00
|
|
|
}
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
case ThiMethod::SetMethod1:
|
|
|
|
LOG_DEBUG(Service_NVDRV, "NVDEC method 0x{:X}",
|
|
|
|
static_cast<u32>(nvdec_thi_state.method_0));
|
2021-06-28 23:54:54 -05:00
|
|
|
nvdec_processor->ProcessMethod(nvdec_thi_state.method_0, data);
|
2020-10-26 22:07:36 -05:00
|
|
|
break;
|
|
|
|
default:
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
case ChClassId::GraphicsVic:
|
2020-12-04 13:39:12 -06:00
|
|
|
ThiStateWrite(vic_thi_state, static_cast<u32>(state_offset), {data});
|
|
|
|
switch (static_cast<ThiMethod>(state_offset)) {
|
2020-10-26 22:07:36 -05:00
|
|
|
case ThiMethod::IncSyncpt: {
|
|
|
|
LOG_DEBUG(Service_NVDRV, "VIC Class IncSyncpt Method");
|
|
|
|
const auto syncpoint_id = static_cast<u32>(data & 0xFF);
|
|
|
|
const auto cond = static_cast<u32>((data >> 8) & 0xFF);
|
|
|
|
if (cond == 0) {
|
2020-12-28 00:02:06 -06:00
|
|
|
sync_manager->Increment(syncpoint_id);
|
2020-10-26 22:07:36 -05:00
|
|
|
} else {
|
2020-12-28 00:02:06 -06:00
|
|
|
sync_manager->SignalDone(
|
|
|
|
sync_manager->IncrementWhenDone(static_cast<u32>(current_class), syncpoint_id));
|
2020-10-26 22:07:36 -05:00
|
|
|
}
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
case ThiMethod::SetMethod1:
|
|
|
|
LOG_DEBUG(Service_NVDRV, "VIC method 0x{:X}, Args=({})",
|
2020-10-28 18:03:35 -05:00
|
|
|
static_cast<u32>(vic_thi_state.method_0), data);
|
2022-01-30 03:31:13 -06:00
|
|
|
vic_processor->ProcessMethod(static_cast<Host1x::Vic::Method>(vic_thi_state.method_0),
|
|
|
|
data);
|
2020-10-26 22:07:36 -05:00
|
|
|
break;
|
|
|
|
default:
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
break;
|
2022-01-30 03:31:13 -06:00
|
|
|
case ChClassId::Control:
|
2020-10-26 22:07:36 -05:00
|
|
|
// This device is mainly for syncpoint synchronization
|
|
|
|
LOG_DEBUG(Service_NVDRV, "Host1X Class Method");
|
2022-01-30 03:31:13 -06:00
|
|
|
host1x_processor->ProcessMethod(static_cast<Host1x::Control::Method>(offset), data);
|
2020-10-26 22:07:36 -05:00
|
|
|
break;
|
|
|
|
default:
|
|
|
|
UNIMPLEMENTED_MSG("Current class not implemented {:X}", static_cast<u32>(current_class));
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2021-01-07 14:56:15 -06:00
|
|
|
void CDmaPusher::ThiStateWrite(ThiRegisters& state, u32 state_offset, u32 argument) {
|
|
|
|
u8* const offset_ptr = reinterpret_cast<u8*>(&state) + sizeof(u32) * state_offset;
|
|
|
|
std::memcpy(offset_ptr, &argument, sizeof(u32));
|
2020-10-26 22:07:36 -05:00
|
|
|
}
|
|
|
|
|
|
|
|
} // namespace Tegra
|