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https://git.suyu.dev/suyu/suyu
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dyncom: Get rid of unnecessary outer-scope variables in InterpreterMainLoop
This commit is contained in:
Lioncash
parent
3ace75a49f
commit
2843d1b98b
1 changed files with 108 additions and 97 deletions
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@ -3967,16 +3967,12 @@ unsigned InterpreterMainLoop(ARMul_State* state) {
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&&INIT_INST_LENGTH,&&END
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};
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#endif
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arm_inst * inst_base;
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unsigned int lop, rop, dst;
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arm_inst* inst_base;
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unsigned int addr;
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unsigned int phys_addr;
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unsigned int last_pc = 0;
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unsigned int num_instrs = 0;
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static unsigned int last_physical_base = 0, last_logical_base = 0;
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int ptr;
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bool single_step = (cpu->NumInstrsToExecute == 1);
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LOAD_NZCVT;
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DISPATCH:
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@ -4071,9 +4067,9 @@ unsigned InterpreterMainLoop(ARMul_State* state) {
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{
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and_inst *inst_cream = (and_inst *)inst_base->component;
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if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
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lop = RN;
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rop = SHIFTER_OPERAND;
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RD = dst = lop & rop;
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u32 lop = RN;
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u32 rop = SHIFTER_OPERAND;
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RD = lop & rop;
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if (inst_cream->S && (inst_cream->Rd == 15)) {
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if (CurrentModeHasSPSR) {
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cpu->Cpsr = cpu->Spsr_copy;
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@ -4081,8 +4077,8 @@ unsigned InterpreterMainLoop(ARMul_State* state) {
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LOAD_NZCVT;
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}
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} else if (inst_cream->S) {
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UPDATE_NFLAG(dst);
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UPDATE_ZFLAG(dst);
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UPDATE_NFLAG(RD);
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UPDATE_ZFLAG(RD);
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UPDATE_CFLAG_WITH_SC;
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}
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if (inst_cream->Rd == 15) {
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@ -4114,12 +4110,12 @@ unsigned InterpreterMainLoop(ARMul_State* state) {
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{
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bic_inst *inst_cream = (bic_inst *)inst_base->component;
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if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
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lop = RN;
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u32 lop = RN;
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if (inst_cream->Rn == 15) {
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lop += 2 * GET_INST_SIZE(cpu);
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}
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rop = SHIFTER_OPERAND;
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RD = dst = lop & (~rop);
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u32 rop = SHIFTER_OPERAND;
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RD = lop & (~rop);
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if ((inst_cream->S) && (inst_cream->Rd == 15)) {
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if (CurrentModeHasSPSR) {
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cpu->Cpsr = cpu->Spsr_copy;
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@ -4127,8 +4123,8 @@ unsigned InterpreterMainLoop(ARMul_State* state) {
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LOAD_NZCVT;
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}
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} else if (inst_cream->S) {
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UPDATE_NFLAG(dst);
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UPDATE_ZFLAG(dst);
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UPDATE_NFLAG(RD);
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UPDATE_ZFLAG(RD);
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UPDATE_CFLAG_WITH_SC;
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}
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if (inst_cream->Rd == 15) {
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@ -4234,15 +4230,17 @@ unsigned InterpreterMainLoop(ARMul_State* state) {
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}
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CMN_INST:
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{
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cmn_inst *inst_cream = (cmn_inst *)inst_base->component;
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if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
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lop = RN;
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rop = SHIFTER_OPERAND;
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dst = lop + rop;
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UPDATE_NFLAG(dst);
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UPDATE_ZFLAG(dst);
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UPDATE_CFLAG(dst, lop, rop);
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UPDATE_VFLAG((int)dst, (int)lop, (int)rop);
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if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
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cmn_inst* const inst_cream = (cmn_inst*)inst_base->component;
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bool carry;
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bool overflow;
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u32 result = AddWithCarry(RN, SHIFTER_OPERAND, 0, &carry, &overflow);
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UPDATE_NFLAG(result);
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UPDATE_ZFLAG(result);
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cpu->CFlag = carry;
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cpu->VFlag = overflow;
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}
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cpu->Reg[15] += GET_INST_SIZE(cpu);
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INC_PC(sizeof(cmn_inst));
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@ -4251,19 +4249,21 @@ unsigned InterpreterMainLoop(ARMul_State* state) {
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}
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CMP_INST:
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{
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if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
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cmp_inst *inst_cream = (cmp_inst *)inst_base->component;
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lop = RN;
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if (inst_cream->Rn == 15) {
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lop += 2 * GET_INST_SIZE(cpu);
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}
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rop = SHIFTER_OPERAND;
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dst = lop - rop;
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if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
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cmp_inst* const inst_cream = (cmp_inst*)inst_base->component;
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UPDATE_NFLAG(dst);
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UPDATE_ZFLAG(dst);
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UPDATE_CFLAG_NOT_BORROW_FROM(lop, rop);
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UPDATE_VFLAG_OVERFLOW_FROM(dst, lop, rop);
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u32 rn_val = RN;
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if (inst_cream->Rn == 15)
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rn_val += 2 * GET_INST_SIZE(cpu);
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bool carry;
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bool overflow;
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u32 result = AddWithCarry(rn_val, ~SHIFTER_OPERAND, 1, &carry, &overflow);
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UPDATE_NFLAG(result);
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UPDATE_ZFLAG(result);
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cpu->CFlag = carry;
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cpu->VFlag = overflow;
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}
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cpu->Reg[15] += GET_INST_SIZE(cpu);
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INC_PC(sizeof(cmp_inst));
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@ -4321,12 +4321,12 @@ unsigned InterpreterMainLoop(ARMul_State* state) {
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{
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eor_inst *inst_cream = (eor_inst *)inst_base->component;
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if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
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lop = RN;
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u32 lop = RN;
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if (inst_cream->Rn == 15) {
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lop += 2 * GET_INST_SIZE(cpu);
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}
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rop = SHIFTER_OPERAND;
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RD = dst = lop ^ rop;
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u32 rop = SHIFTER_OPERAND;
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RD = lop ^ rop;
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if (inst_cream->S && (inst_cream->Rd == 15)) {
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if (CurrentModeHasSPSR) {
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cpu->Cpsr = cpu->Spsr_copy;
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@ -4334,8 +4334,8 @@ unsigned InterpreterMainLoop(ARMul_State* state) {
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LOAD_NZCVT;
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}
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} else if (inst_cream->S) {
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UPDATE_NFLAG(dst);
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UPDATE_ZFLAG(dst);
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UPDATE_NFLAG(RD);
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UPDATE_ZFLAG(RD);
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UPDATE_CFLAG_WITH_SC;
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}
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if (inst_cream->Rd == 15) {
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@ -4852,10 +4852,10 @@ unsigned InterpreterMainLoop(ARMul_State* state) {
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LOG_ERROR(Core_ARM11, "invalid operands for MLA");
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CITRA_IGNORE_EXIT(-1);
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}
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RD = dst = static_cast<uint32_t>((rm * rs + rn) & 0xffffffff);
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RD = static_cast<uint32_t>((rm * rs + rn) & 0xffffffff);
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if (inst_cream->S) {
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UPDATE_NFLAG(dst);
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UPDATE_ZFLAG(dst);
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UPDATE_NFLAG(RD);
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UPDATE_ZFLAG(RD);
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}
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if (inst_cream->Rd == 15) {
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INC_PC(sizeof(mla_inst));
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@ -4871,7 +4871,7 @@ unsigned InterpreterMainLoop(ARMul_State* state) {
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{
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mov_inst *inst_cream = (mov_inst *)inst_base->component;
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if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
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RD = dst = SHIFTER_OPERAND;
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RD = SHIFTER_OPERAND;
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if (inst_cream->S && (inst_cream->Rd == 15)) {
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if (CurrentModeHasSPSR) {
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cpu->Cpsr = cpu->Spsr_copy;
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@ -4879,8 +4879,8 @@ unsigned InterpreterMainLoop(ARMul_State* state) {
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LOAD_NZCVT;
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}
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} else if (inst_cream->S) {
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UPDATE_NFLAG(dst);
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UPDATE_ZFLAG(dst);
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UPDATE_NFLAG(RD);
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UPDATE_ZFLAG(RD);
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UPDATE_CFLAG_WITH_SC;
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}
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if (inst_cream->Rd == 15) {
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@ -5016,10 +5016,10 @@ unsigned InterpreterMainLoop(ARMul_State* state) {
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if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
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uint64_t rm = RM;
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uint64_t rs = RS;
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RD = dst = static_cast<uint32_t>((rm * rs) & 0xffffffff);
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RD = static_cast<uint32_t>((rm * rs) & 0xffffffff);
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if (inst_cream->S) {
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UPDATE_NFLAG(dst);
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UPDATE_ZFLAG(dst);
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UPDATE_NFLAG(RD);
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UPDATE_ZFLAG(RD);
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}
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if (inst_cream->Rd == 15) {
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INC_PC(sizeof(mul_inst));
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@ -5033,9 +5033,11 @@ unsigned InterpreterMainLoop(ARMul_State* state) {
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}
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MVN_INST:
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{
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mvn_inst *inst_cream = (mvn_inst *)inst_base->component;
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if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
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RD = dst = ~SHIFTER_OPERAND;
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if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
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mvn_inst* const inst_cream = (mvn_inst*)inst_base->component;
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RD = ~SHIFTER_OPERAND;
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if (inst_cream->S && (inst_cream->Rd == 15)) {
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if (CurrentModeHasSPSR) {
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cpu->Cpsr = cpu->Spsr_copy;
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@ -5043,8 +5045,8 @@ unsigned InterpreterMainLoop(ARMul_State* state) {
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LOAD_NZCVT;
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}
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} else if (inst_cream->S) {
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UPDATE_NFLAG(dst);
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UPDATE_ZFLAG(dst);
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UPDATE_NFLAG(RD);
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UPDATE_ZFLAG(RD);
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UPDATE_CFLAG_WITH_SC;
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}
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if (inst_cream->Rd == 15) {
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@ -5059,11 +5061,13 @@ unsigned InterpreterMainLoop(ARMul_State* state) {
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}
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ORR_INST:
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{
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orr_inst *inst_cream = (orr_inst *)inst_base->component;
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if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
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lop = RN;
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rop = SHIFTER_OPERAND;
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RD = dst = lop | rop;
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if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
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orr_inst* const inst_cream = (orr_inst*)inst_base->component;
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u32 lop = RN;
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u32 rop = SHIFTER_OPERAND;
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RD = lop | rop;
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if (inst_cream->S && (inst_cream->Rd == 15)) {
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if (CurrentModeHasSPSR) {
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cpu->Cpsr = cpu->Spsr_copy;
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@ -5071,8 +5075,8 @@ unsigned InterpreterMainLoop(ARMul_State* state) {
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LOAD_NZCVT;
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}
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} else if (inst_cream->S) {
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UPDATE_NFLAG(dst);
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UPDATE_ZFLAG(dst);
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UPDATE_NFLAG(RD);
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UPDATE_ZFLAG(RD);
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UPDATE_CFLAG_WITH_SC;
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}
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if (inst_cream->Rd == 15) {
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@ -5292,14 +5296,17 @@ unsigned InterpreterMainLoop(ARMul_State* state) {
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RFE_INST:
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RSB_INST:
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{
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rsb_inst *inst_cream = (rsb_inst *)inst_base->component;
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if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
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rop = RN;
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lop = SHIFTER_OPERAND;
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if (inst_cream->Rn == 15) {
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rop += 2 * GET_INST_SIZE(cpu);;
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}
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RD = dst = lop - rop;
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if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
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rsb_inst* const inst_cream = (rsb_inst*)inst_base->component;
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u32 rn_val = RN;
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if (inst_cream->Rn == 15)
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rn_val += 2 * GET_INST_SIZE(cpu);
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bool carry;
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bool overflow;
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RD = AddWithCarry(~rn_val, SHIFTER_OPERAND, 1, &carry, &overflow);
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if (inst_cream->S && (inst_cream->Rd == 15)) {
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if (CurrentModeHasSPSR) {
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cpu->Cpsr = cpu->Spsr_copy;
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@ -5307,10 +5314,10 @@ unsigned InterpreterMainLoop(ARMul_State* state) {
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LOAD_NZCVT;
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}
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} else if (inst_cream->S) {
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UPDATE_NFLAG(dst);
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UPDATE_ZFLAG(dst);
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UPDATE_CFLAG_NOT_BORROW_FROM(lop, rop);
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UPDATE_VFLAG_OVERFLOW_FROM(dst, lop, rop);
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UPDATE_NFLAG(RD);
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UPDATE_ZFLAG(RD);
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cpu->CFlag = carry;
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cpu->VFlag = overflow;
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}
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if (inst_cream->Rd == 15) {
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INC_PC(sizeof(rsb_inst));
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@ -5324,11 +5331,13 @@ unsigned InterpreterMainLoop(ARMul_State* state) {
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}
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RSC_INST:
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{
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rsc_inst *inst_cream = (rsc_inst *)inst_base->component;
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if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
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lop = RN;
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rop = SHIFTER_OPERAND;
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RD = dst = rop - lop - !cpu->CFlag;
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if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
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rsc_inst* const inst_cream = (rsc_inst*)inst_base->component;
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bool carry;
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bool overflow;
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RD = AddWithCarry(~RN, SHIFTER_OPERAND, cpu->CFlag, &carry, &overflow);
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if (inst_cream->S && (inst_cream->Rd == 15)) {
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if (CurrentModeHasSPSR) {
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cpu->Cpsr = cpu->Spsr_copy;
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@ -5336,10 +5345,10 @@ unsigned InterpreterMainLoop(ARMul_State* state) {
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LOAD_NZCVT;
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}
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} else if (inst_cream->S) {
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UPDATE_NFLAG(dst);
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UPDATE_ZFLAG(dst);
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UPDATE_CFLAG_NOT_BORROW_FROM_FLAG(rop, lop, !cpu->CFlag);
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UPDATE_VFLAG_OVERFLOW_FROM((int)dst, (int)rop, (int)lop);
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UPDATE_NFLAG(RD);
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UPDATE_ZFLAG(RD);
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cpu->CFlag = carry;
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cpu->VFlag = overflow;
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}
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if (inst_cream->Rd == 15) {
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INC_PC(sizeof(rsc_inst));
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@ -6406,18 +6415,19 @@ unsigned InterpreterMainLoop(ARMul_State* state) {
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TEQ_INST:
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{
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if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
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teq_inst *inst_cream = (teq_inst *)inst_base->component;
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lop = RN;
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if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
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teq_inst* const inst_cream = (teq_inst*)inst_base->component;
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u32 lop = RN;
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u32 rop = SHIFTER_OPERAND;
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if (inst_cream->Rn == 15)
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lop += GET_INST_SIZE(cpu) * 2;
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rop = SHIFTER_OPERAND;
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dst = lop ^ rop;
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u32 result = lop ^ rop;
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UPDATE_NFLAG(dst);
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UPDATE_ZFLAG(dst);
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UPDATE_NFLAG(result);
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UPDATE_ZFLAG(result);
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UPDATE_CFLAG_WITH_SC;
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}
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cpu->Reg[15] += GET_INST_SIZE(cpu);
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@ -6427,18 +6437,19 @@ unsigned InterpreterMainLoop(ARMul_State* state) {
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}
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TST_INST:
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{
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if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
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tst_inst *inst_cream = (tst_inst *)inst_base->component;
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lop = RN;
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if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
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tst_inst* const inst_cream = (tst_inst*)inst_base->component;
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u32 lop = RN;
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u32 rop = SHIFTER_OPERAND;
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if (inst_cream->Rn == 15)
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lop += GET_INST_SIZE(cpu) * 2;
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rop = SHIFTER_OPERAND;
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dst = lop & rop;
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u32 result = lop & rop;
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UPDATE_NFLAG(dst);
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UPDATE_ZFLAG(dst);
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UPDATE_NFLAG(result);
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UPDATE_ZFLAG(result);
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UPDATE_CFLAG_WITH_SC;
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}
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cpu->Reg[15] += GET_INST_SIZE(cpu);
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