sneedmca/suyu
1
0
Fork 0
mirror of https://git.suyu.dev/suyu/suyu synced 2024-11-01 04:47:53 +00:00
Code Issues Projects Releases Packages Wiki Activity Actions 1

shader: Remove IAbs64

Browse source
This commit is contained in:
ReinUsesLisp 2021-06-22 18:28:21 -03:00 committed by ameerj
parent bc6e399ae3
commit 4397053d5c
9 changed files with 3 additions and 26 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

1
src/shader_recompiler/backend/glasm/emit_glasm_instructions.h
View file

@ -306,7 +306,6 @@ void EmitIMul32(EmitContext& ctx, IR::Inst& inst, ScalarS32 a, ScalarS32 b);
void EmitINeg32(EmitContext& ctx, IR::Inst& inst, ScalarS32 value);
void EmitINeg64(EmitContext& ctx, IR::Inst& inst, Register value);
void EmitIAbs32(EmitContext& ctx, IR::Inst& inst, ScalarS32 value);
void EmitIAbs64(EmitContext& ctx, IR::Inst& inst, Register value);
void EmitShiftLeftLogical32(EmitContext& ctx, IR::Inst& inst, ScalarU32 base, ScalarU32 shift);
void EmitShiftLeftLogical64(EmitContext& ctx, IR::Inst& inst, ScalarRegister base, ScalarU32 shift);
void EmitShiftRightLogical32(EmitContext& ctx, IR::Inst& inst, ScalarU32 base, ScalarU32 shift);

4
src/shader_recompiler/backend/glasm/emit_glasm_integer.cpp
View file

@ -82,10 +82,6 @@ void EmitIAbs32(EmitContext& ctx, IR::Inst& inst, ScalarS32 value) {
ctx.Add("ABS.S {},{};", inst, value);
}
void EmitIAbs64(EmitContext& ctx, IR::Inst& inst, Register value) {
ctx.LongAdd("MOV.S64 {},|{}|;", inst, value);
}
void EmitShiftLeftLogical32(EmitContext& ctx, IR::Inst& inst, ScalarU32 base, ScalarU32 shift) {
ctx.Add("SHL.U {}.x,{},{};", inst, base, shift);
}

1
src/shader_recompiler/backend/glsl/emit_glsl_instructions.h
View file

@ -365,7 +365,6 @@ void EmitIMul32(EmitContext& ctx, IR::Inst& inst, std::string_view a, std::strin
void EmitINeg32(EmitContext& ctx, IR::Inst& inst, std::string_view value);
void EmitINeg64(EmitContext& ctx, IR::Inst& inst, std::string_view value);
void EmitIAbs32(EmitContext& ctx, IR::Inst& inst, std::string_view value);
void EmitIAbs64(EmitContext& ctx, IR::Inst& inst, std::string_view value);
void EmitShiftLeftLogical32(EmitContext& ctx, IR::Inst& inst, std::string_view base,
std::string_view shift);
void EmitShiftLeftLogical64(EmitContext& ctx, IR::Inst& inst, std::string_view base,

4
src/shader_recompiler/backend/glsl/emit_glsl_integer.cpp
View file

@ -80,10 +80,6 @@ void EmitIAbs32(EmitContext& ctx, IR::Inst& inst, std::string_view value) {
ctx.AddU32("{}=abs(int({}));", inst, value);
}
void EmitIAbs64(EmitContext& ctx, IR::Inst& inst, std::string_view value) {
ctx.AddU64("{}=abs(int64_t({}));", inst, value);
}
void EmitShiftLeftLogical32(EmitContext& ctx, IR::Inst& inst, std::string_view base,
std::string_view shift) {
ctx.AddU32("{}={}<<{};", inst, base, shift);

1
src/shader_recompiler/backend/spirv/emit_spirv_instructions.h
View file

@ -284,7 +284,6 @@ Id EmitIMul32(EmitContext& ctx, Id a, Id b);
Id EmitINeg32(EmitContext& ctx, Id value);
Id EmitINeg64(EmitContext& ctx, Id value);
Id EmitIAbs32(EmitContext& ctx, Id value);
Id EmitIAbs64(EmitContext& ctx, Id value);
Id EmitShiftLeftLogical32(EmitContext& ctx, Id base, Id shift);
Id EmitShiftLeftLogical64(EmitContext& ctx, Id base, Id shift);
Id EmitShiftRightLogical32(EmitContext& ctx, Id base, Id shift);

4
src/shader_recompiler/backend/spirv/emit_spirv_integer.cpp
View file

@ -84,10 +84,6 @@ Id EmitIAbs32(EmitContext& ctx, Id value) {
return ctx.OpSAbs(ctx.U32[1], value);
}
Id EmitIAbs64(EmitContext& ctx, Id value) {
return ctx.OpSAbs(ctx.U64, value);
}
Id EmitShiftLeftLogical32(EmitContext& ctx, Id base, Id shift) {
return ctx.OpShiftLeftLogical(ctx.U32[1], base, shift);
}

11
src/shader_recompiler/frontend/ir/ir_emitter.cpp
View file

@ -1152,15 +1152,8 @@ U32U64 IREmitter::INeg(const U32U64& value) {
}
}
U32U64 IREmitter::IAbs(const U32U64& value) {
switch (value.Type()) {
case Type::U32:
return Inst<U32>(Opcode::IAbs32, value);
case Type::U64:
return Inst<U64>(Opcode::IAbs64, value);
default:
ThrowInvalidType(value.Type());
}
U32 IREmitter::IAbs(const U32& value) {
return Inst<U32>(Opcode::IAbs32, value);
}
U32U64 IREmitter::ShiftLeftLogical(const U32U64& base, const U32& shift) {

2
src/shader_recompiler/frontend/ir/ir_emitter.h
View file

@ -208,7 +208,7 @@ public:
[[nodiscard]] U32U64 ISub(const U32U64& a, const U32U64& b);
[[nodiscard]] U32 IMul(const U32& a, const U32& b);
[[nodiscard]] U32U64 INeg(const U32U64& value);
[[nodiscard]] U32U64 IAbs(const U32U64& value);
[[nodiscard]] U32 IAbs(const U32& value);
[[nodiscard]] U32U64 ShiftLeftLogical(const U32U64& base, const U32& shift);
[[nodiscard]] U32U64 ShiftRightLogical(const U32U64& base, const U32& shift);
[[nodiscard]] U32U64 ShiftRightArithmetic(const U32U64& base, const U32& shift);

1
src/shader_recompiler/frontend/ir/opcodes.inc
View file

@ -289,7 +289,6 @@ OPCODE(IMul32, U32, U32,
OPCODE(INeg32, U32, U32, )
OPCODE(INeg64, U64, U64, )
OPCODE(IAbs32, U32, U32, )
OPCODE(IAbs64, U64, U64, )
OPCODE(ShiftLeftLogical32, U32, U32, U32, )
OPCODE(ShiftLeftLogical64, U64, U64, U32, )
OPCODE(ShiftRightLogical32, U32, U32, U32, )