Merge pull request #8729 from merryhime/cp15-barriers

arm_dynarmic_cp15: Implement CP15DMB/CP15DSB/CP15ISB

src/core/arm/dynarmic/arm_dynarmic_cp15.cpp

@@ -8,6 +8,10 @@
 #include "core/core.h"
 #include "core/core_timing.h"
 
+#ifdef _MSC_VER
+#include <intrin.h>
+#endif
+
 using Callback = Dynarmic::A32::Coprocessor::Callback;
 using CallbackOrAccessOneWord = Dynarmic::A32::Coprocessor::CallbackOrAccessOneWord;
 using CallbackOrAccessTwoWords = Dynarmic::A32::Coprocessor::CallbackOrAccessTwoWords;
@@ -47,12 +51,31 @@ CallbackOrAccessOneWord DynarmicCP15::CompileSendOneWord(bool two, unsigned opc1
         switch (opc2) {
         case 4:
             // CP15_DATA_SYNC_BARRIER
-            // This is a dummy write, we ignore the value written here.
+            return Callback{
-            return &dummy_value;
+                [](Dynarmic::A32::Jit*, void*, std::uint32_t, std::uint32_t) -> std::uint64_t {
+#ifdef _MSC_VER
+                    _mm_mfence();
+                    _mm_lfence();
+#else
+                    asm volatile("mfence\n\tlfence\n\t" : : : "memory");
+#endif
+                    return 0;
+                },
+                std::nullopt,
+            };
         case 5:
             // CP15_DATA_MEMORY_BARRIER
-            // This is a dummy write, we ignore the value written here.
+            return Callback{
-            return &dummy_value;
+                [](Dynarmic::A32::Jit*, void*, std::uint32_t, std::uint32_t) -> std::uint64_t {
+#ifdef _MSC_VER
+                    _mm_mfence();
+#else
+                    asm volatile("mfence\n\t" : : : "memory");
+#endif
+                    return 0;
+                },
+                std::nullopt,
+            };
         }
     }
 

src/core/arm/dynarmic/arm_dynarmic_cp15.h

@@ -35,6 +35,8 @@ public:
     ARM_Dynarmic_32& parent;
     u32 uprw = 0;
     u32 uro = 0;
+
+    friend class ARM_Dynarmic_32;
 };
 
 } // namespace Core