mirror of
https://git.suyu.dev/suyu/suyu
synced 2024-10-30 11:57:51 +00:00
shader_recompiler: Remove S32 IR type
The frontend IR opcodes do not distinguish between signed and unsigned integer types. Fixes broken shaders when IR validation/graphics debugging is enabled for shaders that used BitCastS32F32
This commit is contained in:
parent
f99f618d45
commit
93cc6e4d99
13 changed files with 19 additions and 46 deletions
|
@ -43,10 +43,6 @@ void EmitBitCastU64F64(EmitContext&, IR::Inst& inst, const IR::Value& value) {
|
|||
Alias(inst, value);
|
||||
}
|
||||
|
||||
void EmitBitCastS32F32(EmitContext&, IR::Inst& inst, const IR::Value& value) {
|
||||
Alias(inst, value);
|
||||
}
|
||||
|
||||
void EmitBitCastF16U16(EmitContext&, IR::Inst& inst, const IR::Value& value) {
|
||||
Alias(inst, value);
|
||||
}
|
||||
|
|
|
@ -197,7 +197,6 @@ void EmitSelectF64(EmitContext& ctx, ScalarS32 cond, Register true_value, Regist
|
|||
void EmitBitCastU16F16(EmitContext& ctx, IR::Inst& inst, const IR::Value& value);
|
||||
void EmitBitCastU32F32(EmitContext& ctx, IR::Inst& inst, const IR::Value& value);
|
||||
void EmitBitCastU64F64(EmitContext& ctx, IR::Inst& inst, const IR::Value& value);
|
||||
void EmitBitCastS32F32(EmitContext& ctx, IR::Inst& inst, const IR::Value& value);
|
||||
void EmitBitCastF16U16(EmitContext& ctx, IR::Inst& inst, const IR::Value& value);
|
||||
void EmitBitCastF32U32(EmitContext& ctx, IR::Inst& inst, const IR::Value& value);
|
||||
void EmitBitCastF64U64(EmitContext& ctx, IR::Inst& inst, const IR::Value& value);
|
||||
|
|
|
@ -48,10 +48,6 @@ void EmitBitCastU64F64(EmitContext& ctx, IR::Inst& inst, std::string_view value)
|
|||
ctx.AddU64("{}=doubleBitsToUint64({});", inst, value);
|
||||
}
|
||||
|
||||
void EmitBitCastS32F32(EmitContext& ctx, IR::Inst& inst, std::string_view value) {
|
||||
ctx.AddF32("{}=ftoi({});", inst, value);
|
||||
}
|
||||
|
||||
void EmitBitCastF16U16([[maybe_unused]] EmitContext& ctx, [[maybe_unused]] IR::Inst& inst) {
|
||||
NotImplemented();
|
||||
}
|
||||
|
|
|
@ -231,7 +231,6 @@ void EmitSelectF64(EmitContext& ctx, IR::Inst& inst, std::string_view cond,
|
|||
void EmitBitCastU16F16(EmitContext& ctx, IR::Inst& inst);
|
||||
void EmitBitCastU32F32(EmitContext& ctx, IR::Inst& inst, std::string_view value);
|
||||
void EmitBitCastU64F64(EmitContext& ctx, IR::Inst& inst, std::string_view value);
|
||||
void EmitBitCastS32F32(EmitContext& ctx, IR::Inst& inst, std::string_view value);
|
||||
void EmitBitCastF16U16(EmitContext& ctx, IR::Inst& inst);
|
||||
void EmitBitCastF32U32(EmitContext& ctx, IR::Inst& inst, std::string_view value);
|
||||
void EmitBitCastF64U64(EmitContext& ctx, IR::Inst& inst, std::string_view value);
|
||||
|
|
|
@ -18,10 +18,6 @@ void EmitBitCastU64F64(EmitContext&) {
|
|||
throw NotImplementedException("SPIR-V Instruction");
|
||||
}
|
||||
|
||||
void EmitBitCastS32F32(EmitContext&) {
|
||||
throw NotImplementedException("SPIR-V Instruction");
|
||||
}
|
||||
|
||||
void EmitBitCastF16U16(EmitContext&) {
|
||||
throw NotImplementedException("SPIR-V Instruction");
|
||||
}
|
||||
|
|
|
@ -179,7 +179,6 @@ Id EmitSelectF64(EmitContext& ctx, Id cond, Id true_value, Id false_value);
|
|||
void EmitBitCastU16F16(EmitContext& ctx);
|
||||
Id EmitBitCastU32F32(EmitContext& ctx, Id value);
|
||||
void EmitBitCastU64F64(EmitContext& ctx);
|
||||
void EmitBitCastS32F32(EmitContext& ctx);
|
||||
void EmitBitCastF16U16(EmitContext&);
|
||||
Id EmitBitCastF32U32(EmitContext& ctx, Id value);
|
||||
void EmitBitCastF64U64(EmitContext& ctx);
|
||||
|
|
|
@ -703,11 +703,6 @@ IR::U32 IREmitter::BitCast<IR::U32, IR::F32>(const IR::F32& value) {
|
|||
return Inst<IR::U32>(Opcode::BitCastU32F32, value);
|
||||
}
|
||||
|
||||
template <>
|
||||
IR::S32 IREmitter::BitCast<IR::S32, IR::F32>(const IR::F32& value) {
|
||||
return Inst<IR::S32>(Opcode::BitCastS32F32, value);
|
||||
}
|
||||
|
||||
template <>
|
||||
IR::F32 IREmitter::BitCast<IR::F32, IR::U32>(const IR::U32& value) {
|
||||
return Inst<IR::F32>(Opcode::BitCastF32U32, value);
|
||||
|
|
|
@ -38,7 +38,6 @@ constexpr Type U8{Type::U8};
|
|||
constexpr Type U16{Type::U16};
|
||||
constexpr Type U32{Type::U32};
|
||||
constexpr Type U64{Type::U64};
|
||||
constexpr Type S32{Type::S32};
|
||||
constexpr Type F16{Type::F16};
|
||||
constexpr Type F32{Type::F32};
|
||||
constexpr Type F64{Type::F64};
|
||||
|
|
|
@ -175,7 +175,6 @@ OPCODE(SelectF64, F64, U1,
|
|||
OPCODE(BitCastU16F16, U16, F16, )
|
||||
OPCODE(BitCastU32F32, U32, F32, )
|
||||
OPCODE(BitCastU64F64, U64, F64, )
|
||||
OPCODE(BitCastS32F32, S32, F32, )
|
||||
OPCODE(BitCastF16U16, F16, U16, )
|
||||
OPCODE(BitCastF32U32, F32, U32, )
|
||||
OPCODE(BitCastF64U64, F64, U64, )
|
||||
|
|
|
@ -24,22 +24,21 @@ enum class Type {
|
|||
U16 = 1 << 7,
|
||||
U32 = 1 << 8,
|
||||
U64 = 1 << 9,
|
||||
S32 = 1 << 10,
|
||||
F16 = 1 << 11,
|
||||
F32 = 1 << 12,
|
||||
F64 = 1 << 13,
|
||||
U32x2 = 1 << 14,
|
||||
U32x3 = 1 << 15,
|
||||
U32x4 = 1 << 16,
|
||||
F16x2 = 1 << 17,
|
||||
F16x3 = 1 << 18,
|
||||
F16x4 = 1 << 19,
|
||||
F32x2 = 1 << 20,
|
||||
F32x3 = 1 << 21,
|
||||
F32x4 = 1 << 22,
|
||||
F64x2 = 1 << 23,
|
||||
F64x3 = 1 << 24,
|
||||
F64x4 = 1 << 25,
|
||||
F16 = 1 << 10,
|
||||
F32 = 1 << 11,
|
||||
F64 = 1 << 12,
|
||||
U32x2 = 1 << 13,
|
||||
U32x3 = 1 << 14,
|
||||
U32x4 = 1 << 15,
|
||||
F16x2 = 1 << 16,
|
||||
F16x3 = 1 << 17,
|
||||
F16x4 = 1 << 18,
|
||||
F32x2 = 1 << 19,
|
||||
F32x3 = 1 << 20,
|
||||
F32x4 = 1 << 21,
|
||||
F64x2 = 1 << 22,
|
||||
F64x3 = 1 << 23,
|
||||
F64x4 = 1 << 24,
|
||||
};
|
||||
DECLARE_ENUM_FLAG_OPERATORS(Type)
|
||||
|
||||
|
|
|
@ -23,8 +23,6 @@ Value::Value(u16 value) noexcept : type{Type::U16}, imm_u16{value} {}
|
|||
|
||||
Value::Value(u32 value) noexcept : type{Type::U32}, imm_u32{value} {}
|
||||
|
||||
Value::Value(s32 value) noexcept : type{Type::S32}, imm_s32{value} {}
|
||||
|
||||
Value::Value(f32 value) noexcept : type{Type::F32}, imm_f32{value} {}
|
||||
|
||||
Value::Value(u64 value) noexcept : type{Type::U64}, imm_u64{value} {}
|
||||
|
@ -71,7 +69,6 @@ bool Value::operator==(const Value& other) const {
|
|||
return imm_u16 == other.imm_u16;
|
||||
case Type::U32:
|
||||
case Type::F32:
|
||||
case Type::S32:
|
||||
return imm_u32 == other.imm_u32;
|
||||
case Type::U64:
|
||||
case Type::F64:
|
||||
|
|
|
@ -268,7 +268,6 @@ using U8 = TypedValue<Type::U8>;
|
|||
using U16 = TypedValue<Type::U16>;
|
||||
using U32 = TypedValue<Type::U32>;
|
||||
using U64 = TypedValue<Type::U64>;
|
||||
using S32 = TypedValue<Type::S32>;
|
||||
using F16 = TypedValue<Type::F16>;
|
||||
using F32 = TypedValue<Type::F32>;
|
||||
using F64 = TypedValue<Type::F64>;
|
||||
|
|
|
@ -486,10 +486,10 @@ void PatchTexelFetch(IR::Block& block, IR::Inst& inst, TexturePixelFormat pixel_
|
|||
const IR::F32 w(ir.CompositeExtract(new_inst, 3));
|
||||
const IR::F16F32F64 max_value(ir.Imm32(get_max_value()));
|
||||
const IR::Value converted =
|
||||
ir.CompositeConstruct(ir.FPMul(ir.ConvertSToF(32, 32, ir.BitCast<IR::S32>(x)), max_value),
|
||||
ir.FPMul(ir.ConvertSToF(32, 32, ir.BitCast<IR::S32>(y)), max_value),
|
||||
ir.FPMul(ir.ConvertSToF(32, 32, ir.BitCast<IR::S32>(z)), max_value),
|
||||
ir.FPMul(ir.ConvertSToF(32, 32, ir.BitCast<IR::S32>(w)), max_value));
|
||||
ir.CompositeConstruct(ir.FPMul(ir.ConvertSToF(32, 32, ir.BitCast<IR::U32>(x)), max_value),
|
||||
ir.FPMul(ir.ConvertSToF(32, 32, ir.BitCast<IR::U32>(y)), max_value),
|
||||
ir.FPMul(ir.ConvertSToF(32, 32, ir.BitCast<IR::U32>(z)), max_value),
|
||||
ir.FPMul(ir.ConvertSToF(32, 32, ir.BitCast<IR::U32>(w)), max_value));
|
||||
inst.ReplaceUsesWith(converted);
|
||||
}
|
||||
} // Anonymous namespace
|
||||
|
|
Loading…
Reference in a new issue