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https://git.suyu.dev/suyu/suyu
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pica: Implement decoding of basic fragment lighting components.
- Diffuse - Distance attenuation - float16/float20 types - Vertex Shader 'view' output
This commit is contained in:
parent
281bc90ad2
commit
b003075570
5 changed files with 120 additions and 15 deletions
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@ -68,6 +68,8 @@ static void InitScreenCoordinates(OutputVertex& vtx)
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float24 inv_w = float24::FromFloat32(1.f) / vtx.pos.w;
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float24 inv_w = float24::FromFloat32(1.f) / vtx.pos.w;
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vtx.color *= inv_w;
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vtx.color *= inv_w;
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vtx.view *= inv_w;
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vtx.quat *= inv_w;
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vtx.tc0 *= inv_w;
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vtx.tc0 *= inv_w;
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vtx.tc1 *= inv_w;
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vtx.tc1 *= inv_w;
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vtx.tc2 *= inv_w;
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vtx.tc2 *= inv_w;
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@ -241,7 +241,8 @@ struct Regs {
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TextureConfig texture0;
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TextureConfig texture0;
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INSERT_PADDING_WORDS(0x8);
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INSERT_PADDING_WORDS(0x8);
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BitField<0, 4, TextureFormat> texture0_format;
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BitField<0, 4, TextureFormat> texture0_format;
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INSERT_PADDING_WORDS(0x2);
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BitField<0, 1, u32> fragment_lighting_enable;
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INSERT_PADDING_WORDS(0x1);
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TextureConfig texture1;
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TextureConfig texture1;
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BitField<0, 4, TextureFormat> texture1_format;
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BitField<0, 4, TextureFormat> texture1_format;
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INSERT_PADDING_WORDS(0x2);
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INSERT_PADDING_WORDS(0x2);
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@ -645,6 +646,22 @@ struct Regs {
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INSERT_PADDING_WORDS(0x20);
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INSERT_PADDING_WORDS(0x20);
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enum class LightingSampler {
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Distribution0 = 0,
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Distribution1 = 1,
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Fresnel = 3,
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Blue = 4,
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Green = 5,
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Red = 6,
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SpotlightAttenuation = 8,
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DistanceAttenuation = 16,
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};
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enum class LightingLutInput {
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NH = 0, // Cosine of the angle between the normal and half-angle vectors
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LN = 3, // Cosine of the angle between the light and the normal vectors
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};
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struct {
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struct {
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union LightColor {
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union LightColor {
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BitField< 0, 10, u32> b;
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BitField< 0, 10, u32> b;
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@ -664,17 +681,21 @@ struct Regs {
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struct {
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struct {
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// Encoded as 16-bit floating point
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// Encoded as 16-bit floating point
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u16 x;
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union {
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u16 y;
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BitField< 0, 16, u32> x;
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u16 z;
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BitField<16, 16, u32> y;
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u16 unk;
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};
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union {
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BitField< 0, 16, u32> z;
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};
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INSERT_PADDING_WORDS(0x3);
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INSERT_PADDING_WORDS(0x3);
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// 1.f if 0, otherwise 0.f
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union {
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BitField<0, 1, u32> w;
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BitField<0, 1, u32> w; // 1.f if 0, otherwise 0.f
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} position;
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BitField<1, 1, u32> two_sided_diffuse; // when disabled, clamp dot-product to 0
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};
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};
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BitField<0, 20, u32> dist_atten_bias;
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BitField<0, 20, u32> dist_atten_bias;
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BitField<0, 20, u32> dist_atten_scale;
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BitField<0, 20, u32> dist_atten_scale;
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@ -722,7 +743,27 @@ struct Regs {
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// registers is written to, the behavior will be the same.
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// registers is written to, the behavior will be the same.
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u32 lut_data[8];
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u32 lut_data[8];
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INSERT_PADDING_WORDS(0x9);
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union {
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BitField< 1, 1, u32> d0;
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BitField< 5, 1, u32> d1;
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BitField< 9, 1, u32> sp;
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BitField<13, 1, u32> fr;
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BitField<17, 1, u32> rb;
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BitField<21, 1, u32> rg;
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BitField<25, 1, u32> rr;
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} abs_lut_input;
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union {
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BitField< 0, 3, u32> d0;
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BitField< 4, 3, u32> d1;
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BitField< 8, 3, u32> sp;
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BitField<12, 3, u32> fr;
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BitField<16, 3, u32> rb;
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BitField<20, 3, u32> rg;
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BitField<24, 3, u32> rr;
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} lut_input;
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INSERT_PADDING_WORDS(0x7);
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union {
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union {
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// There are 8 light enable "slots", corresponding to the total number of lights
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// There are 8 light enable "slots", corresponding to the total number of lights
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@ -1095,6 +1136,7 @@ ASSERT_REG_POSITION(viewport_corner, 0x68);
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ASSERT_REG_POSITION(texture0_enable, 0x80);
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ASSERT_REG_POSITION(texture0_enable, 0x80);
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ASSERT_REG_POSITION(texture0, 0x81);
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ASSERT_REG_POSITION(texture0, 0x81);
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ASSERT_REG_POSITION(texture0_format, 0x8e);
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ASSERT_REG_POSITION(texture0_format, 0x8e);
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ASSERT_REG_POSITION(fragment_lighting_enable, 0x8f);
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ASSERT_REG_POSITION(texture1, 0x91);
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ASSERT_REG_POSITION(texture1, 0x91);
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ASSERT_REG_POSITION(texture1_format, 0x96);
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ASSERT_REG_POSITION(texture1_format, 0x96);
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ASSERT_REG_POSITION(texture2, 0x99);
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ASSERT_REG_POSITION(texture2, 0x99);
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@ -1109,6 +1151,7 @@ ASSERT_REG_POSITION(tev_stage5, 0xf8);
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ASSERT_REG_POSITION(tev_combiner_buffer_color, 0xfd);
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ASSERT_REG_POSITION(tev_combiner_buffer_color, 0xfd);
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ASSERT_REG_POSITION(output_merger, 0x100);
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ASSERT_REG_POSITION(output_merger, 0x100);
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ASSERT_REG_POSITION(framebuffer, 0x110);
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ASSERT_REG_POSITION(framebuffer, 0x110);
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ASSERT_REG_POSITION(lighting, 0x140);
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ASSERT_REG_POSITION(vertex_attributes, 0x200);
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ASSERT_REG_POSITION(vertex_attributes, 0x200);
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ASSERT_REG_POSITION(index_array, 0x227);
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ASSERT_REG_POSITION(index_array, 0x227);
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ASSERT_REG_POSITION(num_vertices, 0x228);
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ASSERT_REG_POSITION(num_vertices, 0x228);
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@ -121,4 +121,60 @@ private:
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static_assert(sizeof(float24) == sizeof(float), "Shader JIT assumes float24 is implemented as a 32-bit float");
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static_assert(sizeof(float24) == sizeof(float), "Shader JIT assumes float24 is implemented as a 32-bit float");
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struct float16 {
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// 10 bit mantissa, 5 bit exponent, 1 bit sign
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// TODO: No idea if this works as intended
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static float16 FromRawFloat16(u32 hex) {
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float16 ret;
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if ((hex & 0xFFFF) == 0) {
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ret.value = 0;
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} else {
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u32 mantissa = hex & 0x3FF;
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u32 exponent = (hex >> 10) & 0x1F;
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u32 sign = (hex >> 15) & 1;
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ret.value = std::pow(2.0f, (float)exponent - 15.0f) * (1.0f + mantissa * std::pow(2.0f, -10.f));
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if (sign)
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ret.value = -ret.value;
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}
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return ret;
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}
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float ToFloat32() const {
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return value;
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}
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private:
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// Stored as a regular float, merely for convenience
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// TODO: Perform proper arithmetic on this!
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float value;
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};
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struct float20 {
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// 12 bit mantissa, 7 bit exponent, 1 bit sign
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// TODO: No idea if this works as intended
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static float20 FromRawFloat20(u32 hex) {
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float20 ret;
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if ((hex & 0xFFFFF) == 0) {
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ret.value = 0;
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} else {
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u32 mantissa = hex & 0xFFF;
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u32 exponent = (hex >> 12) & 0x7F;
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u32 sign = (hex >> 19) & 1;
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ret.value = std::pow(2.0f, (float)exponent - 63.0f) * (1.0f + mantissa * std::pow(2.0f, -12.f));
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if (sign)
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ret.value = -ret.value;
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}
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return ret;
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}
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float ToFloat32() const {
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return value;
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}
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private:
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// Stored as a regular float, merely for convenience
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// TODO: Perform proper arithmetic on this!
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float value;
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};
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} // namespace Pica
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} // namespace Pica
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@ -134,11 +134,13 @@ OutputVertex Run(UnitState<false>& state, const InputVertex& input, int num_attr
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std::fmin(std::fabs(ret.color[i].ToFloat32()), 1.0f));
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std::fmin(std::fabs(ret.color[i].ToFloat32()), 1.0f));
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}
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}
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LOG_TRACE(Render_Software, "Output vertex: pos (%.2f, %.2f, %.2f, %.2f), quat (%.2f, %.2f, %.2f, %.2f), col(%.2f, %.2f, %.2f, %.2f), tc0(%.2f, %.2f)",
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LOG_TRACE(Render_Software, "Output vertex: pos(%.2f, %.2f, %.2f, %.2f), quat(%.2f, %.2f, %.2f, %.2f), "
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"col(%.2f, %.2f, %.2f, %.2f), tc0(%.2f, %.2f), view(%.2f, %.2f, %.2f)",
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ret.pos.x.ToFloat32(), ret.pos.y.ToFloat32(), ret.pos.z.ToFloat32(), ret.pos.w.ToFloat32(),
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ret.pos.x.ToFloat32(), ret.pos.y.ToFloat32(), ret.pos.z.ToFloat32(), ret.pos.w.ToFloat32(),
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ret.quat.x.ToFloat32(), ret.quat.y.ToFloat32(), ret.quat.z.ToFloat32(), ret.quat.w.ToFloat32(),
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ret.quat.x.ToFloat32(), ret.quat.y.ToFloat32(), ret.quat.z.ToFloat32(), ret.quat.w.ToFloat32(),
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ret.color.x.ToFloat32(), ret.color.y.ToFloat32(), ret.color.z.ToFloat32(), ret.color.w.ToFloat32(),
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ret.color.x.ToFloat32(), ret.color.y.ToFloat32(), ret.color.z.ToFloat32(), ret.color.w.ToFloat32(),
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ret.tc0.u().ToFloat32(), ret.tc0.v().ToFloat32());
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ret.tc0.u().ToFloat32(), ret.tc0.v().ToFloat32(),
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ret.view.x.ToFloat32(), ret.view.y.ToFloat32(), ret.view.z.ToFloat32());
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return ret;
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return ret;
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}
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}
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@ -37,17 +37,19 @@ struct OutputVertex {
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Math::Vec4<float24> color;
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Math::Vec4<float24> color;
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Math::Vec2<float24> tc0;
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Math::Vec2<float24> tc0;
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Math::Vec2<float24> tc1;
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Math::Vec2<float24> tc1;
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float24 pad[6];
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INSERT_PADDING_WORDS(2);
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Math::Vec3<float24> view;
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INSERT_PADDING_WORDS(1);
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Math::Vec2<float24> tc2;
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Math::Vec2<float24> tc2;
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// Padding for optimal alignment
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// Padding for optimal alignment
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float24 pad2[4];
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INSERT_PADDING_WORDS(4);
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// Attributes used to store intermediate results
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// Attributes used to store intermediate results
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// position after perspective divide
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// position after perspective divide
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Math::Vec3<float24> screenpos;
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Math::Vec3<float24> screenpos;
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float24 pad3;
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INSERT_PADDING_WORDS(1);
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// Linear interpolation
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// Linear interpolation
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// factor: 0=this, 1=vtx
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// factor: 0=this, 1=vtx
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