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MaxwellDMA: Implement BlockLinear to BlockLinear copies.
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2 changed files with 69 additions and 1 deletions
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@ -62,7 +62,8 @@ void MaxwellDMA::Launch() {
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if (!is_src_pitch && !is_dst_pitch) {
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if (!is_src_pitch && !is_dst_pitch) {
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// If both the source and the destination are in block layout, assert.
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// If both the source and the destination are in block layout, assert.
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UNIMPLEMENTED_MSG("Tiled->Tiled DMA transfers are not yet implemented");
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CopyBlockLinearToBlockLinear();
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ReleaseSemaphore();
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return;
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return;
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}
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}
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@ -291,6 +292,70 @@ void MaxwellDMA::FastCopyBlockLinearToPitch() {
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memory_manager.WriteBlock(regs.offset_out, write_buffer.data(), dst_size);
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memory_manager.WriteBlock(regs.offset_out, write_buffer.data(), dst_size);
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}
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}
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void MaxwellDMA::CopyBlockLinearToBlockLinear() {
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UNIMPLEMENTED_IF(regs.src_params.block_size.width != 0);
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const bool is_remapping = regs.launch_dma.remap_enable != 0;
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// Deswizzle the input and copy it over.
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const Parameters& src = regs.src_params;
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const Parameters& dst = regs.dst_params;
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const u32 num_remap_components = regs.remap_const.num_dst_components_minus_one + 1;
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const u32 remap_components_size = regs.remap_const.component_size_minus_one + 1;
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const u32 base_bpp = !is_remapping ? 1U : num_remap_components * remap_components_size;
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u32 src_width = src.width;
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u32 dst_width = dst.width;
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u32 x_elements = regs.line_length_in;
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u32 src_x_offset = src.origin.x;
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u32 dst_x_offset = dst.origin.x;
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u32 bpp_shift = 0U;
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if (!is_remapping) {
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bpp_shift = Common::FoldRight(
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4U, [](u32 x, u32 y) { return std::min(x, static_cast<u32>(std::countr_zero(y))); },
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src_width, dst_width, x_elements, src_x_offset, dst_x_offset,
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static_cast<u32>(regs.offset_in), static_cast<u32>(regs.offset_out));
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src_width >>= bpp_shift;
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dst_width >>= bpp_shift;
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x_elements >>= bpp_shift;
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src_x_offset >>= bpp_shift;
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dst_x_offset >>= bpp_shift;
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}
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const u32 bytes_per_pixel = base_bpp << bpp_shift;
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const size_t src_size = CalculateSize(true, bytes_per_pixel, src_width, src.height, src.depth,
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src.block_size.height, src.block_size.depth);
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const size_t dst_size = CalculateSize(true, bytes_per_pixel, dst_width, dst.height, dst.depth,
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dst.block_size.height, dst.block_size.depth);
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const u32 pitch = x_elements * bytes_per_pixel;
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const size_t mid_buffer_size = pitch * regs.line_count;
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if (read_buffer.size() < src_size) {
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read_buffer.resize(src_size);
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}
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if (write_buffer.size() < dst_size) {
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write_buffer.resize(dst_size);
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}
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intermediate_buffer.resize(mid_buffer_size);
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memory_manager.ReadBlock(regs.offset_in, read_buffer.data(), src_size);
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memory_manager.ReadBlock(regs.offset_out, write_buffer.data(), dst_size);
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UnswizzleSubrect(intermediate_buffer, read_buffer, bytes_per_pixel, src_width, src.height,
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src.depth, src_x_offset, src.origin.y, x_elements, regs.line_count,
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src.block_size.height, src.block_size.depth, pitch);
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SwizzleSubrect(write_buffer, intermediate_buffer, bytes_per_pixel, dst_width, dst.height,
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dst.depth, dst_x_offset, dst.origin.y, x_elements, regs.line_count,
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dst.block_size.height, dst.block_size.depth, pitch);
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memory_manager.WriteBlock(regs.offset_out, write_buffer.data(), dst_size);
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}
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void MaxwellDMA::ReleaseSemaphore() {
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void MaxwellDMA::ReleaseSemaphore() {
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const auto type = regs.launch_dma.semaphore_type;
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const auto type = regs.launch_dma.semaphore_type;
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const GPUVAddr address = regs.semaphore.address;
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const GPUVAddr address = regs.semaphore.address;
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@ -223,6 +223,8 @@ private:
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void CopyPitchToBlockLinear();
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void CopyPitchToBlockLinear();
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void CopyBlockLinearToBlockLinear();
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void FastCopyBlockLinearToPitch();
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void FastCopyBlockLinearToPitch();
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void ReleaseSemaphore();
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void ReleaseSemaphore();
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@ -234,6 +236,7 @@ private:
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std::vector<u8> read_buffer;
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std::vector<u8> read_buffer;
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std::vector<u8> write_buffer;
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std::vector<u8> write_buffer;
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std::vector<u8> intermediate_buffer;
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static constexpr std::size_t NUM_REGS = 0x800;
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static constexpr std::size_t NUM_REGS = 0x800;
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struct Regs {
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struct Regs {
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