sneedmca/suyu
1
0
Fork 0
mirror of https://git.suyu.dev/suyu/suyu synced 2024-12-24 10:23:01 -06:00
Code Issues Projects Releases Packages Wiki Activity Actions 1

shader: Properly blacklist and scale image loads

Browse source
This commit is contained in:
ReinUsesLisp 2021-08-01 02:26:02 -03:00 committed by Fernando Sahmkow
parent c7a1cbad44
commit fc9bb3c3fe
5 changed files with 31 additions and 11 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

22
src/shader_recompiler/ir_opt/rescaling_pass.cpp
View file

@ -84,10 +84,8 @@ void PatchImageQueryDimensions(IR::Block& block, IR::Inst& inst) {
} }
} }
void PatchImageFetch(IR::Block& block, IR::Inst& inst) { void ScaleIntegerCoord(IR::IREmitter& ir, IR::Inst& inst, const IR::U1& is_scaled) {
IR::IREmitter ir{block, IR::Block::InstructionList::s_iterator_to(inst)};
const auto info{inst.Flags<IR::TextureInstInfo>()}; const auto info{inst.Flags<IR::TextureInstInfo>()};
const IR::U1 is_scaled{ir.IsTextureScaled(ir.Imm32(info.descriptor_index))};
const IR::Value coord{inst.Arg(1)}; const IR::Value coord{inst.Arg(1)};
switch (info.type) { switch (info.type) {
case TextureType::Color1D: case TextureType::Color1D:
@ -121,6 +119,21 @@ void PatchImageFetch(IR::Block& block, IR::Inst& inst) {
} }
} }
void PatchImageFetch(IR::Block& block, IR::Inst& inst) {
IR::IREmitter ir{block, IR::Block::InstructionList::s_iterator_to(inst)};
const auto info{inst.Flags<IR::TextureInstInfo>()};
const IR::U1 is_scaled{ir.IsTextureScaled(ir.Imm32(info.descriptor_index))};
ScaleIntegerCoord(ir, inst, is_scaled);
}
void PatchImageRead(IR::Block& block, IR::Inst& inst) {
IR::IREmitter ir{block, IR::Block::InstructionList::s_iterator_to(inst)};
const auto info{inst.Flags<IR::TextureInstInfo>()};
// TODO: Scale conditionally
const IR::U1 is_scaled{IR::Value{true}};
ScaleIntegerCoord(ir, inst, is_scaled);
}
void Visit(const IR::Program& program, IR::Block& block, IR::Inst& inst) { void Visit(const IR::Program& program, IR::Block& block, IR::Inst& inst) {
const bool is_fragment_shader{program.stage == Stage::Fragment}; const bool is_fragment_shader{program.stage == Stage::Fragment};
switch (inst.GetOpcode()) { switch (inst.GetOpcode()) {
@ -144,6 +157,9 @@ void Visit(const IR::Program& program, IR::Block& block, IR::Inst& inst) {
case IR::Opcode::ImageFetch: case IR::Opcode::ImageFetch:
PatchImageFetch(block, inst); PatchImageFetch(block, inst);
break; break;
case IR::Opcode::ImageRead:
PatchImageRead(block, inst);
break;
default: default:
break; break;
} }

2
src/video_core/renderer_opengl/gl_compute_pipeline.cpp
View file

@ -139,7 +139,7 @@ void ComputePipeline::Configure() {
} }
} }
for (const auto& desc : info.image_descriptors) { for (const auto& desc : info.image_descriptors) {
add_image(desc, true); add_image(desc, desc.is_written);
} }
texture_cache.FillComputeImageViews(std::span(views.data(), views.size())); texture_cache.FillComputeImageViews(std::span(views.data(), views.size()));

2
src/video_core/renderer_opengl/gl_graphics_pipeline.cpp
View file

@ -362,7 +362,7 @@ void GraphicsPipeline::ConfigureImpl(bool is_indexed) {
} }
if constexpr (Spec::has_images) { if constexpr (Spec::has_images) {
for (const auto& desc : info.image_descriptors) { for (const auto& desc : info.image_descriptors) {
add_image(desc, true); add_image(desc, desc.is_written);
} }
} }
}}; }};

2
src/video_core/renderer_vulkan/vk_compute_pipeline.cpp
View file

@ -159,7 +159,7 @@ void ComputePipeline::Configure(Tegra::Engines::KeplerCompute& kepler_compute,
} }
} }
for (const auto& desc : info.image_descriptors) { for (const auto& desc : info.image_descriptors) {
add_image(desc, true); add_image(desc, desc.is_written);
} }
texture_cache.FillComputeImageViews(std::span(views.data(), views.size())); texture_cache.FillComputeImageViews(std::span(views.data(), views.size()));

14
src/video_core/renderer_vulkan/vk_graphics_pipeline.cpp
View file

@ -322,20 +322,24 @@ void GraphicsPipeline::ConfigureImpl(bool is_indexed) {
} }
return TexturePair(gpu_memory.Read<u32>(addr), via_header_index); return TexturePair(gpu_memory.Read<u32>(addr), via_header_index);
}}; }};
const auto add_image{[&](const auto& desc) { const auto add_image{[&](const auto& desc, bool blacklist) LAMBDA_FORCEINLINE {
for (u32 index = 0; index < desc.count; ++index) { for (u32 index = 0; index < desc.count; ++index) {
const auto handle{read_handle(desc, index)}; const auto handle{read_handle(desc, index)};
views[view_index++] = {handle.first}; views[view_index++] = {
.index = handle.first,
.blacklist = blacklist,
.id = {},
};
} }
}}; }};
if constexpr (Spec::has_texture_buffers) { if constexpr (Spec::has_texture_buffers) {
for (const auto& desc : info.texture_buffer_descriptors) { for (const auto& desc : info.texture_buffer_descriptors) {
add_image(desc); add_image(desc, false);
} }
} }
if constexpr (Spec::has_image_buffers) { if constexpr (Spec::has_image_buffers) {
for (const auto& desc : info.image_buffer_descriptors) { for (const auto& desc : info.image_buffer_descriptors) {
add_image(desc); add_image(desc, false);
} }
} }
for (const auto& desc : info.texture_descriptors) { for (const auto& desc : info.texture_descriptors) {
@ -349,7 +353,7 @@ void GraphicsPipeline::ConfigureImpl(bool is_indexed) {
} }
if constexpr (Spec::has_images) { if constexpr (Spec::has_images) {
for (const auto& desc : info.image_descriptors) { for (const auto& desc : info.image_descriptors) {
add_image(desc); add_image(desc, desc.is_written);
} }
} }
}}; }};