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https://git.suyu.dev/suyu/suyu
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Merge pull request #1003 from lioncash/armcruft
dyncom: Minor cleanups.
This commit is contained in:
bunnei
commit
fe15cf0019
6 changed files with 91 additions and 124 deletions
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@ -5,7 +5,7 @@
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#include "core/arm/dyncom/arm_dyncom_dec.h"
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#include "core/arm/skyeye_common/armsupp.h"
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const ISEITEM arm_instruction[] = {
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const InstructionSetEncodingItem arm_instruction[] = {
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{ "vmla", 4, ARMVFP2, { 23, 27, 0x1C, 20, 21, 0x0, 9, 11, 0x5, 4, 4, 0 }},
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{ "vmls", 7, ARMVFP2, { 28, 31, 0xF, 25, 27, 0x1, 23, 23, 1, 11, 11, 0, 8, 9, 0x2, 6, 6, 1, 4, 4, 0 }},
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{ "vnmla", 4, ARMVFP2, { 23, 27, 0x1C, 20, 21, 0x1, 9, 11, 0x5, 4, 4, 0 }},
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@ -207,7 +207,7 @@ const ISEITEM arm_instruction[] = {
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{ "bbl", 1, 0, { 25, 27, 0x00000005 }},
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};
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const ISEITEM arm_exclusion_code[] = {
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const InstructionSetEncodingItem arm_exclusion_code[] = {
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{ "vmla", 0, ARMVFP2, { 0 }},
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{ "vmls", 0, ARMVFP2, { 0 }},
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{ "vnmla", 0, ARMVFP2, { 0 }},
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@ -414,14 +414,13 @@ const ISEITEM arm_exclusion_code[] = {
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{ "invalid", 0, INVALID, { 0 }}
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};
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int decode_arm_instr(u32 instr, s32* idx) {
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ARMDecodeStatus DecodeARMInstruction(u32 instr, s32* idx) {
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int n = 0;
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int base = 0;
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int ret = DECODE_FAILURE;
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int i = 0;
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int instr_slots = sizeof(arm_instruction) / sizeof(ISEITEM);
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int instr_slots = sizeof(arm_instruction) / sizeof(InstructionSetEncodingItem);
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ARMDecodeStatus ret = ARMDecodeStatus::FAILURE;
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for (i = 0; i < instr_slots; i++) {
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for (int i = 0; i < instr_slots; i++) {
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n = arm_instruction[i].attribute_value;
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base = 0;
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@ -438,11 +437,11 @@ int decode_arm_instr(u32 instr, s32* idx) {
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n--;
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}
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// All conditions is satisfied.
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// All conditions are satisfied.
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if (n == 0)
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ret = DECODE_SUCCESS;
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ret = ARMDecodeStatus::SUCCESS;
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if (ret == DECODE_SUCCESS) {
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if (ret == ARMDecodeStatus::SUCCESS) {
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n = arm_exclusion_code[i].attribute_value;
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if (n != 0) {
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base = 0;
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@ -454,13 +453,13 @@ int decode_arm_instr(u32 instr, s32* idx) {
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n--;
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}
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// All conditions is satisfied.
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// All conditions are satisfied.
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if (n == 0)
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ret = DECODE_FAILURE;
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ret = ARMDecodeStatus::FAILURE;
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}
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}
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if (ret == DECODE_SUCCESS) {
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if (ret == ARMDecodeStatus::SUCCESS) {
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*idx = i;
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return ret;
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}
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@ -6,22 +6,20 @@
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#include "common/common_types.h"
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int decode_arm_instr(u32 instr, s32* idx);
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enum DECODE_STATUS {
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DECODE_SUCCESS,
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DECODE_FAILURE
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enum class ARMDecodeStatus {
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SUCCESS,
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FAILURE
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};
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struct instruction_set_encoding_item {
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ARMDecodeStatus DecodeARMInstruction(u32 instr, s32* idx);
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struct InstructionSetEncodingItem {
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const char *name;
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int attribute_value;
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int version;
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u32 content[21];
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};
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typedef struct instruction_set_encoding_item ISEITEM;
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// ARM versions
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enum {
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INVALID = 0,
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@ -38,4 +36,4 @@ enum {
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ARMV6K,
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};
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extern const ISEITEM arm_instruction[];
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extern const InstructionSetEncodingItem arm_instruction[];
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@ -47,27 +47,6 @@ enum {
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typedef unsigned int (*shtop_fp_t)(ARMul_State* cpu, unsigned int sht_oper);
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// Defines a reservation granule of 2 words, which protects the first 2 words starting at the tag.
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// This is the smallest granule allowed by the v7 spec, and is coincidentally just large enough to
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// support LDR/STREXD.
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static const u32 RESERVATION_GRANULE_MASK = 0xFFFFFFF8;
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// Exclusive memory access
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static int exclusive_detect(ARMul_State* state, u32 addr) {
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if(state->exclusive_tag == (addr & RESERVATION_GRANULE_MASK))
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return 0;
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else
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return -1;
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}
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static void add_exclusive_addr(ARMul_State* state, u32 addr){
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state->exclusive_tag = addr & RESERVATION_GRANULE_MASK;
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}
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static void remove_exclusive(ARMul_State* state, u32 addr){
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state->exclusive_tag = 0xFFFFFFFF;
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}
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static int CondPassed(ARMul_State* cpu, unsigned int cond) {
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const u32 NFLAG = cpu->NFlag;
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const u32 ZFLAG = cpu->ZFlag;
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@ -3489,21 +3468,15 @@ enum {
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FETCH_FAILURE
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};
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static tdstate decode_thumb_instr(u32 inst, u32 addr, u32* arm_inst, u32* inst_size, ARM_INST_PTR* ptr_inst_base) {
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static ThumbDecodeStatus DecodeThumbInstruction(u32 inst, u32 addr, u32* arm_inst, u32* inst_size, ARM_INST_PTR* ptr_inst_base) {
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// Check if in Thumb mode
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tdstate ret = thumb_translate (addr, inst, arm_inst, inst_size);
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if(ret == t_branch){
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// TODO: FIXME, endian should be judged
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u32 tinstr;
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if((addr & 0x3) != 0)
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tinstr = inst >> 16;
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else
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tinstr = inst & 0xFFFF;
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ThumbDecodeStatus ret = TranslateThumbInstruction (addr, inst, arm_inst, inst_size);
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if (ret == ThumbDecodeStatus::BRANCH) {
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int inst_index;
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int table_length = sizeof(arm_instruction_trans) / sizeof(transop_fp_t);
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u32 tinstr = GetThumbInstruction(inst, addr);
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switch((tinstr & 0xF800) >> 11){
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switch ((tinstr & 0xF800) >> 11) {
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case 26:
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case 27:
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if (((tinstr & 0x0F00) != 0x0E00) && ((tinstr & 0x0F00) != 0x0F00)){
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@ -3536,7 +3509,7 @@ static tdstate decode_thumb_instr(u32 inst, u32 addr, u32* arm_inst, u32* inst_s
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*ptr_inst_base = arm_instruction_trans[inst_index](tinstr, inst_index);
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break;
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default:
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ret = t_undefined;
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ret = ThumbDecodeStatus::UNDEFINED;
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break;
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}
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}
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@ -3548,10 +3521,6 @@ enum {
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FETCH_EXCEPTION
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};
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typedef struct instruction_set_encoding_item ISEITEM;
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extern const ISEITEM arm_instruction[];
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static int InterpreterTranslate(ARMul_State* cpu, int& bb_start, u32 addr) {
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Common::Profiling::ScopeTimer timer_decode(profile_decode);
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@ -3573,20 +3542,19 @@ static int InterpreterTranslate(ARMul_State* cpu, int& bb_start, u32 addr) {
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inst = Memory::Read32(phys_addr & 0xFFFFFFFC);
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size++;
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// If we are in thumb instruction, we will translate one thumb to one corresponding arm instruction
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// If we are in Thumb mode, we'll translate one Thumb instruction to the corresponding ARM instruction
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if (cpu->TFlag) {
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uint32_t arm_inst;
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tdstate state = decode_thumb_instr(inst, phys_addr, &arm_inst, &inst_size, &inst_base);
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ThumbDecodeStatus state = DecodeThumbInstruction(inst, phys_addr, &arm_inst, &inst_size, &inst_base);
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// We have translated the branch instruction of thumb in thumb decoder
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if(state == t_branch){
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// We have translated the Thumb branch instruction in the Thumb decoder
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if (state == ThumbDecodeStatus::BRANCH) {
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goto translated;
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}
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inst = arm_inst;
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}
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ret = decode_arm_instr(inst, &idx);
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if (ret == DECODE_FAILURE) {
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if (DecodeARMInstruction(inst, &idx) == ARMDecodeStatus::FAILURE) {
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std::string disasm = ARM_Disasm::Disassemble(phys_addr, inst);
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LOG_ERROR(Core_ARM11, "Decode failure.\tPC : [0x%x]\tInstruction : %s [%x]", phys_addr, disasm.c_str(), inst);
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LOG_ERROR(Core_ARM11, "cpsr=0x%x, cpu->TFlag=%d, r15=0x%x", cpu->Cpsr, cpu->TFlag, cpu->Reg[15]);
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@ -4174,9 +4142,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
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CLREX_INST:
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{
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remove_exclusive(cpu, 0);
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cpu->exclusive_state = 0;
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cpu->UnsetExclusiveMemoryAddress();
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cpu->Reg[15] += cpu->GetInstructionSize();
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INC_PC(sizeof(clrex_inst));
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FETCH_INST;
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@ -4543,8 +4509,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
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generic_arm_inst* inst_cream = (generic_arm_inst*)inst_base->component;
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unsigned int read_addr = RN;
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add_exclusive_addr(cpu, read_addr);
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cpu->exclusive_state = 1;
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cpu->SetExclusiveMemoryAddress(read_addr);
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RD = cpu->ReadMemory32(read_addr);
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if (inst_cream->Rd == 15) {
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@ -4563,8 +4528,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
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generic_arm_inst* inst_cream = (generic_arm_inst*)inst_base->component;
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unsigned int read_addr = RN;
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add_exclusive_addr(cpu, read_addr);
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cpu->exclusive_state = 1;
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cpu->SetExclusiveMemoryAddress(read_addr);
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RD = Memory::Read8(read_addr);
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if (inst_cream->Rd == 15) {
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@ -4583,8 +4547,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
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generic_arm_inst* inst_cream = (generic_arm_inst*)inst_base->component;
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unsigned int read_addr = RN;
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add_exclusive_addr(cpu, read_addr);
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cpu->exclusive_state = 1;
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cpu->SetExclusiveMemoryAddress(read_addr);
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RD = cpu->ReadMemory16(read_addr);
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if (inst_cream->Rd == 15) {
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@ -4603,8 +4566,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
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generic_arm_inst* inst_cream = (generic_arm_inst*)inst_base->component;
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unsigned int read_addr = RN;
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add_exclusive_addr(cpu, read_addr);
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cpu->exclusive_state = 1;
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cpu->SetExclusiveMemoryAddress(read_addr);
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RD = cpu->ReadMemory32(read_addr);
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RD2 = cpu->ReadMemory32(read_addr + 4);
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@ -6089,10 +6051,8 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
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generic_arm_inst* inst_cream = (generic_arm_inst*)inst_base->component;
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unsigned int write_addr = cpu->Reg[inst_cream->Rn];
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if ((exclusive_detect(cpu, write_addr) == 0) && (cpu->exclusive_state == 1)) {
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remove_exclusive(cpu, write_addr);
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cpu->exclusive_state = 0;
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if (cpu->IsExclusiveMemoryAccess(write_addr)) {
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cpu->UnsetExclusiveMemoryAddress();
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cpu->WriteMemory32(write_addr, RM);
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RD = 0;
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} else {
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@ -6111,10 +6071,8 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
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generic_arm_inst* inst_cream = (generic_arm_inst*)inst_base->component;
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unsigned int write_addr = cpu->Reg[inst_cream->Rn];
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if ((exclusive_detect(cpu, write_addr) == 0) && (cpu->exclusive_state == 1)) {
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remove_exclusive(cpu, write_addr);
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cpu->exclusive_state = 0;
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if (cpu->IsExclusiveMemoryAccess(write_addr)) {
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cpu->UnsetExclusiveMemoryAddress();
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Memory::Write8(write_addr, cpu->Reg[inst_cream->Rm]);
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RD = 0;
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} else {
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@ -6133,9 +6091,8 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
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generic_arm_inst* inst_cream = (generic_arm_inst*)inst_base->component;
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unsigned int write_addr = cpu->Reg[inst_cream->Rn];
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if ((exclusive_detect(cpu, write_addr) == 0) && (cpu->exclusive_state == 1)) {
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remove_exclusive(cpu, write_addr);
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cpu->exclusive_state = 0;
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if (cpu->IsExclusiveMemoryAccess(write_addr)) {
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cpu->UnsetExclusiveMemoryAddress();
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const u32 rt = cpu->Reg[inst_cream->Rm + 0];
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const u32 rt2 = cpu->Reg[inst_cream->Rm + 1];
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@ -6165,10 +6122,8 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
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generic_arm_inst* inst_cream = (generic_arm_inst*)inst_base->component;
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unsigned int write_addr = cpu->Reg[inst_cream->Rn];
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if ((exclusive_detect(cpu, write_addr) == 0) && (cpu->exclusive_state == 1)) {
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remove_exclusive(cpu, write_addr);
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cpu->exclusive_state = 0;
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if (cpu->IsExclusiveMemoryAccess(write_addr)) {
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cpu->UnsetExclusiveMemoryAddress();
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cpu->WriteMemory16(write_addr, RM);
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RD = 0;
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} else {
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@ -12,15 +12,9 @@
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// with the following Thumb instruction held in the high 16-bits. Passing in two Thumb instructions
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// allows easier simulation of the special dual BL instruction.
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tdstate thumb_translate(u32 addr, u32 instr, u32* ainstr, u32* inst_size) {
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tdstate valid = t_uninitialized;
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u32 tinstr = instr;
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// The endian should be judge here
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if((addr & 0x3) != 0)
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tinstr = instr >> 16;
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else
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tinstr &= 0xFFFF;
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ThumbDecodeStatus TranslateThumbInstruction(u32 addr, u32 instr, u32* ainstr, u32* inst_size) {
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ThumbDecodeStatus valid = ThumbDecodeStatus::UNINITIALIZED;
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u32 tinstr = GetThumbInstruction(instr, addr);
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*ainstr = 0xDEADC0DE; // Debugging to catch non updates
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@ -357,21 +351,21 @@ tdstate thumb_translate(u32 addr, u32 instr, u32* ainstr, u32* inst_size) {
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else
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*ainstr |= (tinstr & 0x00FF);
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} else if ((tinstr & 0x0F00) != 0x0E00)
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valid = t_branch;
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valid = ThumbDecodeStatus::BRANCH;
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else // UNDEFINED : cc=1110(AL) uses different format
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valid = t_undefined;
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valid = ThumbDecodeStatus::UNDEFINED;
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break;
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case 28: // B
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valid = t_branch;
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valid = ThumbDecodeStatus::BRANCH;
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break;
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case 29:
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if(tinstr & 0x1)
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valid = t_undefined;
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if (tinstr & 0x1)
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valid = ThumbDecodeStatus::UNDEFINED;
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else
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valid = t_branch;
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valid = ThumbDecodeStatus::BRANCH;
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break;
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case 30: // BL instruction 1
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@ -380,7 +374,7 @@ tdstate thumb_translate(u32 addr, u32 instr, u32* ainstr, u32* inst_size) {
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// simulation simple (from the user perspective) we check if the following instruction is
|
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// the second half of this BL, and if it is we simulate it immediately
|
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valid = t_branch;
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valid = ThumbDecodeStatus::BRANCH;
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break;
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case 31: // BL instruction 2
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|
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@ -389,7 +383,7 @@ tdstate thumb_translate(u32 addr, u32 instr, u32* ainstr, u32* inst_size) {
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// ever be matched with the fmt19 "BL instruction 1" instruction. However, we do allow the
|
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// simulation of it on its own, with undefined results if r14 is not suitably initialised.
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valid = t_branch;
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valid = ThumbDecodeStatus::BRANCH;
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break;
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}
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|
|
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|
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@ -28,20 +28,22 @@
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#include "common/common_types.h"
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|
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enum tdstate {
|
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t_undefined, // Undefined Thumb instruction
|
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t_decoded, // Instruction decoded to ARM equivalent
|
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t_branch, // Thumb branch (already processed)
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t_uninitialized,
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enum class ThumbDecodeStatus {
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UNDEFINED, // Undefined Thumb instruction
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DECODED, // Instruction decoded to ARM equivalent
|
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BRANCH, // Thumb branch (already processed)
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UNINITIALIZED,
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};
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tdstate thumb_translate(u32 addr, u32 instr, u32* ainstr, u32* inst_size);
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// Translates a Thumb mode instruction into its ARM equivalent.
|
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ThumbDecodeStatus TranslateThumbInstruction(u32 addr, u32 instr, u32* ainstr, u32* inst_size);
|
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|
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static inline u32 get_thumb_instr(u32 instr, u32 pc) {
|
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u32 tinstr;
|
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if ((pc & 0x3) != 0)
|
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tinstr = instr >> 16;
|
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else
|
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tinstr = instr & 0xFFFF;
|
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return tinstr;
|
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static inline u32 GetThumbInstruction(u32 instr, u32 address) {
|
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// Normally you would need to handle instruction endianness,
|
||||
// however, it is fixed to little-endian on the MPCore, so
|
||||
// there's no need to check for this beforehand.
|
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if ((address & 0x3) != 0)
|
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return instr >> 16;
|
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|
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return instr & 0xFFFF;
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}
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|
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@ -163,6 +163,19 @@ public:
|
|||
u32 ReadCP15Register(u32 crn, u32 opcode_1, u32 crm, u32 opcode_2) const;
|
||||
void WriteCP15Register(u32 value, u32 crn, u32 opcode_1, u32 crm, u32 opcode_2);
|
||||
|
||||
// Exclusive memory access functions
|
||||
bool IsExclusiveMemoryAccess(u32 address) const {
|
||||
return exclusive_state && exclusive_tag == (address & RESERVATION_GRANULE_MASK);
|
||||
}
|
||||
void SetExclusiveMemoryAddress(u32 address) {
|
||||
exclusive_tag = address & RESERVATION_GRANULE_MASK;
|
||||
exclusive_state = true;
|
||||
}
|
||||
void UnsetExclusiveMemoryAddress() {
|
||||
exclusive_tag = 0xFFFFFFFF;
|
||||
exclusive_state = false;
|
||||
}
|
||||
|
||||
// Whether or not the given CPU is in big endian mode (E bit is set)
|
||||
bool InBigEndianMode() const {
|
||||
return (Cpsr & (1 << 9)) != 0;
|
||||
|
|
@ -203,9 +216,6 @@ public:
|
|||
|
||||
u32 Mode; // The current mode
|
||||
u32 Bank; // The current register bank
|
||||
u32 exclusive_tag; // The address for which the local monitor is in exclusive access mode
|
||||
u32 exclusive_state;
|
||||
u32 exclusive_result;
|
||||
|
||||
u32 NFlag, ZFlag, CFlag, VFlag, IFFlags; // Dummy flags for speed
|
||||
unsigned int shifter_carry_out;
|
||||
|
|
@ -230,4 +240,13 @@ public:
|
|||
|
||||
private:
|
||||
void ResetMPCoreCP15Registers();
|
||||
|
||||
// Defines a reservation granule of 2 words, which protects the first 2 words starting at the tag.
|
||||
// This is the smallest granule allowed by the v7 spec, and is coincidentally just large enough to
|
||||
// support LDR/STREXD.
|
||||
static const u32 RESERVATION_GRANULE_MASK = 0xFFFFFFF8;
|
||||
|
||||
u32 exclusive_tag; // The address for which the local monitor is in exclusive access mode
|
||||
u32 exclusive_result;
|
||||
bool exclusive_state;
|
||||
};
|
||||
|
|
|
|||
Loading…
Reference in a new issue