Commit graph

731 commits

Author SHA1 Message Date
merry
7f11710e0a dynarmic: Print stack trace on unrecognised instruction or other exception 2022-04-05 20:40:20 +01:00
bunnei
f114436120
Merge pull request #8089 from merryhime/paranoia
configuration: Add Paranoid CPU accuracy level
2022-04-04 11:07:38 -07:00
merry
1383441b15 arm_dynarmic_64: Invalidate on all cores 2022-03-27 15:37:19 +01:00
merry
3c8547160d configuration: Add Paranoid CPU accuracy level
Disables most optimizations for the paranoid.
2022-03-26 08:46:25 +00:00
bunnei
e439c31c9e
Revert "dynarmic: Reduce size of code caches" 2022-03-22 18:32:54 -07:00
ameerj
ade596121b core: Reduce unused includes 2022-03-19 02:23:32 -04:00
Merry
220674d0d6 dynarmic: Reduce size of code caches 2022-03-13 22:17:14 +00:00
merry
16784e5bb3 dynarmic: Inline exclusive memory accesses
Inlines implementation of exclusive instructions into JITted code,
improving performance of applications relying heavily on these
instructions.

We also fastmem these instructions for additional speed, with
support for appropriate recompilation on fastmem failure.

An unsafe optimization to disable the intercore global_monitor is also
provided, should one wish to rely solely on cmpxchg semantics for
safety.

See also: merryhime/dynarmic#664
2022-02-27 19:40:05 +00:00
Lioncash
f785f73e92 general: Replace NonCopyable struct with equivalents 2022-02-02 13:17:12 -05:00
jam1garner
4d9c9e567e arm: dynarmic: Cleanup icache op handling 2021-11-21 22:44:13 -05:00
jam1garner
c8a67a725d arm: dynarmic: Implement icache op handling for 'ic iallu' instruction 2021-11-21 21:18:56 -05:00
jam1garner
84eb3e7d02 arm: dynarmic: Implement icache op handling for 'ic ivau' instruction 2021-11-21 21:10:14 -05:00
ameerj
7c4b6aab2e core: Remove unused includes 2021-11-03 21:42:57 -04:00
Andrew Strelsky
31b9797296
Fixed ARM_Dynamic_64 Step 2021-10-24 11:16:32 -04:00
lat9nq
dc06e11a7b settings, arm_dynarmic, yuzu qt: Move CPU debugging option
Decouples the CPU debugging mode from the enumeration to its own
boolean. After this, it moves the CPU Debugging tab over to a sub tab
underneath the Debug tab in the configuration UI.
2021-07-08 16:56:44 -04:00
lat9nq
eebf39b3c0 arm_dynarmic_64: Re-add fastmem_address_space_bits to Auto setting 2021-07-08 15:14:45 -04:00
lat9nq
87b6e14d7c arm_dynarmic{32,64}: Fixes from test build
Now sets optimizations regardless of the Settings. Drops unsafe fastmem
optimization.
2021-07-08 14:56:09 -04:00
lat9nq
7ab5767157 core,common,yuzu qt: Add CPU accuracy option 'Auto'
The current CPU accuracy settings in yuzu are fairly polarized and
require more than common knowledge to know what the optimal settings for
yuzu would be. This adds a curated option called 'Auto' that applies a
few at the moment known-good unsafe optimizations to Dynarmic.
2021-07-08 14:56:09 -04:00
Wunkolo
4569f39c7c common: Replace common_sizes into user-literals
Removes common_sizes.h in favor of having `_KiB`, `_MiB`, `_GiB`, etc
user-literals within literals.h.

To keep the global namespace clean, users will have to use:

```
using namespace Common::Literals;
```

to access these literals.
2021-06-24 09:27:40 -07:00
Fernando Sahmkow
2298508465 Update dynarmic and add new unsafe CPU option. 2021-06-20 20:40:02 +02:00
FernandoS27
5ba28325b2 General: Add settings for fastmem and disabling adress space check. 2021-06-11 17:27:17 +02:00
Markus Wick
621f3f5f47 core: Make use of fastmem 2021-06-11 17:27:06 +02:00
bunnei
f34176996e
Merge pull request #6385 from degasus/save_memory_access
core/memory: Check our memory fallbacks for out-of-bound behavior.
2021-05-30 23:21:39 -07:00
Markus Wick
ddb186e61d core/arm_interface: Improve the performance of memory fallbacks.
We just create one memory subsystem. This is a constant all the time.
So there is no need to call the non-inlined parent.Memory() helper on every callback.
2021-05-29 09:02:19 +02:00
Markus Wick
d2d7a5060f externals: Update dynarmic.
The new version supports fastmem on a64.
2021-05-29 08:53:01 +02:00
Markus Wick
3d2e80daed core/arm_interface: Call SVC after end of dynarmic block.
So we can modify all of dynarmic states within SVC without ExceptionalExit.

Especially as the ExceptionalExit hack is dropped on upstream dynarmic.
2021-05-27 23:23:23 +02:00
Markus Wick
993dbe49fc core/arm: Drop ChangeProcessorID.
This code was used to switch the CPU ID on thread switches.
However since "hle: kernel: multicore: Replace n-JITs impl. with 4 JITs.", the CPU ID is not a constant.
This has been dead code since this rewrite, and dropped in dynarmic as well. So there is no need to keep it.
2021-05-26 19:48:24 +02:00
bunnei
7626ca3343
Merge pull request #6321 from lat9nq/per-game-cpu
configuration: Add CPU tab to game properties and slight per-game settings rework
2021-05-20 20:10:56 -07:00
Lioncash
9a07ed53eb core: Make variable shadowing a compile-time error
Now that we have most of core free of shadowing, we can enable the
warning as an error to catch anything that may be remaining and also
eliminate this class of logic bug entirely.
2021-05-16 03:43:16 -04:00
lat9nq
e169fdad4f general: Make CPU accuracy and related a Settings::Setting
Required to make CPU accuracy and unsafe settings available to use as a
per-game setting.
2021-05-15 20:46:48 -04:00
bunnei
2a7eff57a8 hle: kernel: Rename Process to KProcess. 2021-05-05 16:40:52 -07:00
Lioncash
9e726a9250 service: Resolve cases of member field shadowing
Now all that remains is for kernel code to be 'shadow-free' and then
-Wshadow can be turned into an error.
2021-05-04 04:38:38 -04:00
Lioncash
ebb64d5bf4 core: Resolve misc cases of variable shadowing
Resolves shadowing warnings that aren't in a particularly large
subsection of core. Brings us closer to turning -Wshadow into an error.

All that remains now is for cases in the kernel (left untouched for now
since a big change by bunnei is pending), and a few left over in the
service code (will be tackled next).
2021-05-03 01:19:13 -04:00
bunnei
a4c6712a4b common: Move settings to common from core.
- Removes a dependency on core and input_common from common.
2021-04-14 16:24:03 -07:00
MerryMage
0fbd7752c3 arm_dynarmic: Increase size of code cache 2021-04-02 18:09:15 +01:00
MerryMage
52dae41d7f arm_dynarmic: Always have a 'valid' jit instance 2021-03-24 18:47:17 +00:00
bunnei
a35717b245 core: arm_dynarmic: Ensure JIT state is saved/restored on page table changes.
- We re-create the JIT here without preserving any state.
2021-03-21 15:25:25 -07:00
MerryMage
821fc4a7b6 arm_dynarmic_32: Print out CPSR.T on exception 2021-02-01 18:35:33 +00:00
bunnei
c8fe8247ee arm: dynarmic: Reintroduce JIT checks on SaveContext/LoadContext. 2021-01-28 21:50:39 -08:00
bunnei
055194d2ab core: arm: Remove unnecessary JIT checks. 2021-01-28 21:42:26 -08:00
bunnei
9a4e148f9e arm: arm_dynarmic: Skip calls when JIT is invalid.
- This can happen if called from an idle or suspension thread.
2021-01-28 21:42:25 -08:00
bunnei
354130cd84 core: arm: arm_interface: Fix shadowing errors. 2021-01-11 14:23:16 -08:00
ReinUsesLisp
b4451c5e81 core: Silence unhandled enum in switch warnings 2021-01-08 23:21:07 -03:00
MerryMage
57c9da1b39 dynarmic: Add Unsafe_InaccurateNaN optimization 2021-01-02 20:13:21 +00:00
ReinUsesLisp
b3587102d1 core/memory: Read and write page table atomically
Squash attributes into the pointer's integer, making them an uintptr_t
pair containing 2 bits at the bottom and then the pointer. These bits
are currently unused thanks to alignment requirements.

Configure Dynarmic to mask out these bits on pointer reads.

While we are at it, remove some unused attributes carried over from
Citra.

Read/Write and other hot functions use a two step unpacking process that
is less readable to stop MSVC from emitting an extra AND instruction in
the hot path:

 mov         rdi,rcx
 shr         rdx,0Ch
 mov         r8,qword ptr [rax+8]
 mov         rax,qword ptr [r8+rdx*8]
 mov         rdx,rax
-and         al,3
 and         rdx,0FFFFFFFFFFFFFFFCh
 je          Core::Memory::Memory::Impl::Read<unsigned char>
 mov         rax,qword ptr [vaddr]
 movzx       eax,byte ptr [rdx+rax]
2020-12-29 21:54:49 -03:00
bunnei
9e29e36a78 hle: kernel: Rewrite scheduler implementation based on Mesopshere. 2020-12-06 00:03:24 -08:00
bunnei
c10a37e5b6 hle: kernel: physical_core: Clear exclusive state after each run.
- This is closer to pre-multicore behavior, and works a bit better.
2020-12-06 00:03:24 -08:00
bunnei
63fd1bb503 core: arm: Implement InvalidateCacheRange for CPU cache invalidation. 2020-11-29 01:31:52 -08:00
bunnei
7b642c7781 hle: kernel: multicore: Replace n-JITs impl. with 4 JITs. 2020-11-29 01:31:51 -08:00
Lioncash
5bc4eabe36 core: Eliminate remaining usages of the global system instance
Removes all remaining usages of the global system instance. After this,
migration can begin to migrate to being constructed and managed entirely
by the various frontends.
2020-11-27 11:40:45 -05:00