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https://git.suyu.dev/suyu/suyu
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114 lines
4 KiB
C++
114 lines
4 KiB
C++
// Copyright 2015 Citra Emulator Project
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// Licensed under GPLv2 or any later version
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// Refer to the license.txt file included.
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#include <cmath>
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#include <cstring>
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#include "common/bit_set.h"
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#include "common/logging/log.h"
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#include "common/microprofile.h"
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#include "video_core/pica_state.h"
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#include "video_core/regs_rasterizer.h"
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#include "video_core/regs_shader.h"
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#include "video_core/shader/shader.h"
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#include "video_core/shader/shader_interpreter.h"
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#ifdef ARCHITECTURE_x86_64
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#include "video_core/shader/shader_jit_x64.h"
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#endif // ARCHITECTURE_x86_64
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#include "video_core/video_core.h"
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namespace Pica {
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namespace Shader {
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OutputVertex OutputVertex::FromAttributeBuffer(const RasterizerRegs& regs, AttributeBuffer& input) {
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// Setup output data
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union {
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OutputVertex ret{};
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std::array<float24, 24> vertex_slots;
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};
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static_assert(sizeof(vertex_slots) == sizeof(ret), "Struct and array have different sizes.");
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unsigned int num_attributes = regs.vs_output_total;
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ASSERT(num_attributes <= 7);
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for (unsigned int i = 0; i < num_attributes; ++i) {
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const auto& output_register_map = regs.vs_output_attributes[i];
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RasterizerRegs::VSOutputAttributes::Semantic semantics[4] = {
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output_register_map.map_x, output_register_map.map_y, output_register_map.map_z,
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output_register_map.map_w};
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for (unsigned comp = 0; comp < 4; ++comp) {
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RasterizerRegs::VSOutputAttributes::Semantic semantic = semantics[comp];
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if (semantic < vertex_slots.size()) {
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vertex_slots[semantic] = input.attr[i][comp];
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} else if (semantic != RasterizerRegs::VSOutputAttributes::INVALID) {
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LOG_ERROR(HW_GPU, "Invalid/unknown semantic id: %u", (unsigned int)semantic);
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}
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}
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}
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// The hardware takes the absolute and saturates vertex colors like this, *before* doing
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// interpolation
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for (unsigned i = 0; i < 4; ++i) {
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ret.color[i] = float24::FromFloat32(std::fmin(std::fabs(ret.color[i].ToFloat32()), 1.0f));
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}
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LOG_TRACE(HW_GPU, "Output vertex: pos(%.2f, %.2f, %.2f, %.2f), quat(%.2f, %.2f, %.2f, %.2f), "
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"col(%.2f, %.2f, %.2f, %.2f), tc0(%.2f, %.2f), view(%.2f, %.2f, %.2f)",
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ret.pos.x.ToFloat32(), ret.pos.y.ToFloat32(), ret.pos.z.ToFloat32(),
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ret.pos.w.ToFloat32(), ret.quat.x.ToFloat32(), ret.quat.y.ToFloat32(),
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ret.quat.z.ToFloat32(), ret.quat.w.ToFloat32(), ret.color.x.ToFloat32(),
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ret.color.y.ToFloat32(), ret.color.z.ToFloat32(), ret.color.w.ToFloat32(),
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ret.tc0.u().ToFloat32(), ret.tc0.v().ToFloat32(), ret.view.x.ToFloat32(),
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ret.view.y.ToFloat32(), ret.view.z.ToFloat32());
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return ret;
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}
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void UnitState::LoadInput(const ShaderRegs& config, const AttributeBuffer& input) {
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const unsigned max_attribute = config.max_input_attribute_index;
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for (unsigned attr = 0; attr <= max_attribute; ++attr) {
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unsigned reg = config.GetRegisterForAttribute(attr);
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registers.input[reg] = input.attr[attr];
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}
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}
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void UnitState::WriteOutput(const ShaderRegs& config, AttributeBuffer& output) {
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unsigned int output_i = 0;
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for (unsigned int reg : Common::BitSet<u32>(config.output_mask)) {
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output.attr[output_i++] = registers.output[reg];
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}
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}
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MICROPROFILE_DEFINE(GPU_Shader, "GPU", "Shader", MP_RGB(50, 50, 240));
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#ifdef ARCHITECTURE_x86_64
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static std::unique_ptr<JitX64Engine> jit_engine;
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#endif // ARCHITECTURE_x86_64
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static InterpreterEngine interpreter_engine;
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ShaderEngine* GetEngine() {
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#ifdef ARCHITECTURE_x86_64
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// TODO(yuriks): Re-initialize on each change rather than being persistent
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if (VideoCore::g_shader_jit_enabled) {
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if (jit_engine == nullptr) {
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jit_engine = std::make_unique<JitX64Engine>();
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}
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return jit_engine.get();
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}
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#endif // ARCHITECTURE_x86_64
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return &interpreter_engine;
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}
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void Shutdown() {
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#ifdef ARCHITECTURE_x86_64
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jit_engine = nullptr;
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#endif // ARCHITECTURE_x86_64
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}
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} // namespace Shader
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} // namespace Pica
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