mirror of
https://git.suyu.dev/suyu/suyu
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4e35177e23
Implement VOTE using Nvidia's intrinsics. Documentation about these can be found here https://developer.nvidia.com/reading-between-threads-shader-intrinsics Instead of using portable ARB instructions I opted to use Nvidia intrinsics because these are the closest we have to how Tegra X1 hardware renders. To stub VOTE on non-Nvidia drivers (including nouveau) this commit simulates a GPU with a warp size of one, returning what is meaningful for the instruction being emulated: * anyThreadNV(value) -> value * allThreadsNV(value) -> value * allThreadsEqualNV(value) -> true ballotARB, also known as "uint64_t(activeThreadsNV())", emits VOTE.ANY Rd, PT, PT; on nouveau's compiler. This doesn't match exactly to Nvidia's code VOTE.ALL Rd, PT, PT; Which is emulated with activeThreadsNV() by this commit. In theory this shouldn't really matter since .ANY, .ALL and .EQ affect the predicates (set to PT on those cases) and not the registers.
1947 lines
57 KiB
C++
1947 lines
57 KiB
C++
// Copyright 2018 yuzu Emulator Project
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// Licensed under GPLv2 or any later version
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// Refer to the license.txt file included.
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#pragma once
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#include <array>
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#include <bitset>
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#include <optional>
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#include <tuple>
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#include <vector>
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#include "common/assert.h"
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#include "common/bit_field.h"
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#include "common/common_types.h"
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namespace Tegra::Shader {
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struct Register {
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/// Number of registers
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static constexpr std::size_t NumRegisters = 256;
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/// Register 255 is special cased to always be 0
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static constexpr std::size_t ZeroIndex = 255;
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enum class Size : u64 {
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Byte = 0,
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Short = 1,
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Word = 2,
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Long = 3,
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};
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constexpr Register() = default;
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constexpr Register(u64 value) : value(value) {}
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constexpr operator u64() const {
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return value;
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}
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template <typename T>
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constexpr u64 operator-(const T& oth) const {
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return value - oth;
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}
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template <typename T>
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constexpr u64 operator&(const T& oth) const {
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return value & oth;
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}
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constexpr u64 operator&(const Register& oth) const {
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return value & oth.value;
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}
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constexpr u64 operator~() const {
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return ~value;
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}
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u64 GetSwizzledIndex(u64 elem) const {
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elem = (value + elem) & 3;
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return (value & ~3) + elem;
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}
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private:
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u64 value{};
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};
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enum class AttributeSize : u64 {
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Word = 0,
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DoubleWord = 1,
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TripleWord = 2,
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QuadWord = 3,
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};
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union Attribute {
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Attribute() = default;
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constexpr explicit Attribute(u64 value) : value(value) {}
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enum class Index : u64 {
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LayerViewportPointSize = 6,
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Position = 7,
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Attribute_0 = 8,
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Attribute_31 = 39,
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ClipDistances0123 = 44,
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ClipDistances4567 = 45,
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PointCoord = 46,
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// This attribute contains a tuple of (~, ~, InstanceId, VertexId) when inside a vertex
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// shader, and a tuple of (TessCoord.x, TessCoord.y, TessCoord.z, ~) when inside a Tess Eval
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// shader.
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TessCoordInstanceIDVertexID = 47,
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// This attribute contains a tuple of (Unk, Unk, Unk, gl_FrontFacing) when inside a fragment
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// shader. It is unknown what the other values contain.
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FrontFacing = 63,
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};
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union {
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BitField<20, 10, u64> immediate;
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BitField<22, 2, u64> element;
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BitField<24, 6, Index> index;
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BitField<47, 3, AttributeSize> size;
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bool IsPhysical() const {
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return element == 0 && static_cast<u64>(index.Value()) == 0;
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}
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} fmt20;
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union {
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BitField<30, 2, u64> element;
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BitField<32, 6, Index> index;
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} fmt28;
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BitField<39, 8, u64> reg;
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u64 value{};
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};
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union Sampler {
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Sampler() = default;
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constexpr explicit Sampler(u64 value) : value(value) {}
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enum class Index : u64 {
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Sampler_0 = 8,
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};
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BitField<36, 13, Index> index;
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u64 value{};
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};
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union Image {
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Image() = default;
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constexpr explicit Image(u64 value) : value{value} {}
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BitField<36, 13, u64> index;
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u64 value;
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};
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} // namespace Tegra::Shader
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namespace std {
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// TODO(bunnei): The below is forbidden by the C++ standard, but works fine. See #330.
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template <>
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struct make_unsigned<Tegra::Shader::Attribute> {
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using type = Tegra::Shader::Attribute;
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};
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template <>
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struct make_unsigned<Tegra::Shader::Register> {
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using type = Tegra::Shader::Register;
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};
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} // namespace std
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namespace Tegra::Shader {
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enum class Pred : u64 {
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UnusedIndex = 0x7,
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NeverExecute = 0xF,
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};
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enum class PredCondition : u64 {
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LessThan = 1,
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Equal = 2,
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LessEqual = 3,
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GreaterThan = 4,
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NotEqual = 5,
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GreaterEqual = 6,
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LessThanWithNan = 9,
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LessEqualWithNan = 11,
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GreaterThanWithNan = 12,
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NotEqualWithNan = 13,
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GreaterEqualWithNan = 14,
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// TODO(Subv): Other condition types
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};
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enum class PredOperation : u64 {
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And = 0,
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Or = 1,
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Xor = 2,
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};
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enum class LogicOperation : u64 {
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And = 0,
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Or = 1,
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Xor = 2,
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PassB = 3,
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};
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enum class SubOp : u64 {
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Cos = 0x0,
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Sin = 0x1,
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Ex2 = 0x2,
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Lg2 = 0x3,
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Rcp = 0x4,
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Rsq = 0x5,
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Sqrt = 0x8,
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};
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enum class F2iRoundingOp : u64 {
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RoundEven = 0,
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Floor = 1,
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Ceil = 2,
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Trunc = 3,
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};
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enum class F2fRoundingOp : u64 {
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None = 0,
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Pass = 3,
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Round = 8,
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Floor = 9,
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Ceil = 10,
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Trunc = 11,
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};
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enum class UniformType : u64 {
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UnsignedByte = 0,
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SignedByte = 1,
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UnsignedShort = 2,
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SignedShort = 3,
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Single = 4,
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Double = 5,
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Quad = 6,
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UnsignedQuad = 7,
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};
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enum class StoreType : u64 {
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Unsigned8 = 0,
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Signed8 = 1,
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Unsigned16 = 2,
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Signed16 = 3,
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Bits32 = 4,
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Bits64 = 5,
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Bits128 = 6,
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};
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enum class IMinMaxExchange : u64 {
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None = 0,
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XLo = 1,
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XMed = 2,
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XHi = 3,
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};
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enum class VideoType : u64 {
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Size16_Low = 0,
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Size16_High = 1,
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Size32 = 2,
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Invalid = 3,
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};
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enum class VmadShr : u64 {
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Shr7 = 1,
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Shr15 = 2,
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};
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enum class XmadMode : u64 {
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None = 0,
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CLo = 1,
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CHi = 2,
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CSfu = 3,
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CBcc = 4,
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};
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enum class IAdd3Mode : u64 {
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None = 0,
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RightShift = 1,
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LeftShift = 2,
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};
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enum class IAdd3Height : u64 {
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None = 0,
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LowerHalfWord = 1,
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UpperHalfWord = 2,
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};
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enum class FlowCondition : u64 {
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Always = 0xF,
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Fcsm_Tr = 0x1C, // TODO(bunnei): What is this used for?
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};
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enum class ConditionCode : u64 {
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F = 0,
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LT = 1,
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EQ = 2,
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LE = 3,
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GT = 4,
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NE = 5,
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GE = 6,
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Num = 7,
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Nan = 8,
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LTU = 9,
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EQU = 10,
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LEU = 11,
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GTU = 12,
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NEU = 13,
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GEU = 14,
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T = 15,
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OFF = 16,
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LO = 17,
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SFF = 18,
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LS = 19,
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HI = 20,
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SFT = 21,
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HS = 22,
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OFT = 23,
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CSM_TA = 24,
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CSM_TR = 25,
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CSM_MX = 26,
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FCSM_TA = 27,
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FCSM_TR = 28,
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FCSM_MX = 29,
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RLE = 30,
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RGT = 31,
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};
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enum class PredicateResultMode : u64 {
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None = 0x0,
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NotZero = 0x3,
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};
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enum class TextureType : u64 {
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Texture1D = 0,
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Texture2D = 1,
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Texture3D = 2,
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TextureCube = 3,
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};
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enum class TextureQueryType : u64 {
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Dimension = 1,
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TextureType = 2,
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SamplePosition = 5,
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Filter = 16,
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LevelOfDetail = 18,
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Wrap = 20,
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BorderColor = 22,
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};
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enum class TextureProcessMode : u64 {
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None = 0,
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LZ = 1, // Load LOD of zero.
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LB = 2, // Load Bias.
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LL = 3, // Load LOD.
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LBA = 6, // Load Bias. The A is unknown, does not appear to differ with LB.
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LLA = 7 // Load LOD. The A is unknown, does not appear to differ with LL.
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};
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enum class TextureMiscMode : u64 {
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DC,
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AOFFI, // Uses Offset
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NDV,
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NODEP,
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MZ,
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PTP,
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};
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enum class SurfaceDataMode : u64 {
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P = 0,
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D_BA = 1,
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};
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enum class OutOfBoundsStore : u64 {
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Ignore = 0,
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Clamp = 1,
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Trap = 2,
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};
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enum class ImageType : u64 {
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Texture1D = 0,
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TextureBuffer = 1,
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Texture1DArray = 2,
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Texture2D = 3,
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Texture2DArray = 4,
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Texture3D = 5,
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};
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enum class IsberdMode : u64 {
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None = 0,
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Patch = 1,
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Prim = 2,
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Attr = 3,
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};
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enum class IsberdShift : u64 { None = 0, U16 = 1, B32 = 2 };
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enum class HalfType : u64 {
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H0_H1 = 0,
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F32 = 1,
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H0_H0 = 2,
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H1_H1 = 3,
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};
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enum class HalfMerge : u64 {
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H0_H1 = 0,
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F32 = 1,
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Mrg_H0 = 2,
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Mrg_H1 = 3,
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};
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enum class HalfPrecision : u64 {
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None = 0,
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FTZ = 1,
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FMZ = 2,
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};
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enum class R2pMode : u64 {
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Pr = 0,
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Cc = 1,
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};
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enum class IpaInterpMode : u64 {
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Pass = 0,
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Multiply = 1,
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Constant = 2,
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Sc = 3,
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};
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enum class IpaSampleMode : u64 {
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Default = 0,
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Centroid = 1,
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Offset = 2,
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};
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enum class LmemLoadCacheManagement : u64 {
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Default = 0,
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LU = 1,
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CI = 2,
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CV = 3,
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};
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enum class StoreCacheManagement : u64 {
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Default = 0,
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CG = 1,
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CS = 2,
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WT = 3,
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};
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struct IpaMode {
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IpaInterpMode interpolation_mode;
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IpaSampleMode sampling_mode;
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bool operator==(const IpaMode& a) const {
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return std::tie(interpolation_mode, sampling_mode) ==
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std::tie(a.interpolation_mode, a.sampling_mode);
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}
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bool operator!=(const IpaMode& a) const {
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return !operator==(a);
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}
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bool operator<(const IpaMode& a) const {
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return std::tie(interpolation_mode, sampling_mode) <
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std::tie(a.interpolation_mode, a.sampling_mode);
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}
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};
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enum class SystemVariable : u64 {
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LaneId = 0x00,
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VirtCfg = 0x02,
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VirtId = 0x03,
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Pm0 = 0x04,
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Pm1 = 0x05,
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Pm2 = 0x06,
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Pm3 = 0x07,
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Pm4 = 0x08,
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Pm5 = 0x09,
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Pm6 = 0x0a,
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Pm7 = 0x0b,
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OrderingTicket = 0x0f,
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PrimType = 0x10,
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InvocationId = 0x11,
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Ydirection = 0x12,
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ThreadKill = 0x13,
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ShaderType = 0x14,
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DirectBeWriteAddressLow = 0x15,
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DirectBeWriteAddressHigh = 0x16,
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DirectBeWriteEnabled = 0x17,
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MachineId0 = 0x18,
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MachineId1 = 0x19,
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MachineId2 = 0x1a,
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MachineId3 = 0x1b,
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Affinity = 0x1c,
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InvocationInfo = 0x1d,
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WscaleFactorXY = 0x1e,
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WscaleFactorZ = 0x1f,
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Tid = 0x20,
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TidX = 0x21,
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TidY = 0x22,
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TidZ = 0x23,
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CtaParam = 0x24,
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CtaIdX = 0x25,
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CtaIdY = 0x26,
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CtaIdZ = 0x27,
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NtId = 0x28,
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CirQueueIncrMinusOne = 0x29,
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Nlatc = 0x2a,
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SmSpaVersion = 0x2c,
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MultiPassShaderInfo = 0x2d,
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LwinHi = 0x2e,
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SwinHi = 0x2f,
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SwinLo = 0x30,
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SwinSz = 0x31,
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SmemSz = 0x32,
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SmemBanks = 0x33,
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LwinLo = 0x34,
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LwinSz = 0x35,
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LmemLosz = 0x36,
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LmemHioff = 0x37,
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EqMask = 0x38,
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LtMask = 0x39,
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LeMask = 0x3a,
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GtMask = 0x3b,
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GeMask = 0x3c,
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RegAlloc = 0x3d,
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CtxAddr = 0x3e, // .fmask = F_SM50
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BarrierAlloc = 0x3e, // .fmask = F_SM60
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GlobalErrorStatus = 0x40,
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WarpErrorStatus = 0x42,
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WarpErrorStatusClear = 0x43,
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PmHi0 = 0x48,
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PmHi1 = 0x49,
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PmHi2 = 0x4a,
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PmHi3 = 0x4b,
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PmHi4 = 0x4c,
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PmHi5 = 0x4d,
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PmHi6 = 0x4e,
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PmHi7 = 0x4f,
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ClockLo = 0x50,
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ClockHi = 0x51,
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GlobalTimerLo = 0x52,
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GlobalTimerHi = 0x53,
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HwTaskId = 0x60,
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CircularQueueEntryIndex = 0x61,
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CircularQueueEntryAddressLow = 0x62,
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CircularQueueEntryAddressHigh = 0x63,
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};
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enum class PhysicalAttributeDirection : u64 {
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Input = 0,
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Output = 1,
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};
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enum class VoteOperation : u64 {
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All = 0, // allThreadsNV
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Any = 1, // anyThreadNV
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Eq = 2, // allThreadsEqualNV
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};
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union Instruction {
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Instruction& operator=(const Instruction& instr) {
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value = instr.value;
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return *this;
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}
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constexpr Instruction(u64 value) : value{value} {}
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BitField<0, 8, Register> gpr0;
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BitField<8, 8, Register> gpr8;
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union {
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BitField<16, 4, Pred> full_pred;
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BitField<16, 3, u64> pred_index;
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} pred;
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BitField<19, 1, u64> negate_pred;
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BitField<20, 8, Register> gpr20;
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BitField<20, 4, SubOp> sub_op;
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BitField<28, 8, Register> gpr28;
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BitField<39, 8, Register> gpr39;
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BitField<48, 16, u64> opcode;
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union {
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BitField<8, 5, ConditionCode> cc;
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BitField<13, 1, u64> trigger;
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} nop;
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union {
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BitField<48, 2, VoteOperation> operation;
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BitField<45, 3, u64> dest_pred;
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BitField<39, 3, u64> value;
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BitField<42, 1, u64> negate_value;
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} vote;
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|
union {
|
|
BitField<8, 8, Register> gpr;
|
|
BitField<20, 24, s64> offset;
|
|
} gmem;
|
|
|
|
union {
|
|
BitField<20, 16, u64> imm20_16;
|
|
BitField<20, 19, u64> imm20_19;
|
|
BitField<20, 32, s64> imm20_32;
|
|
BitField<45, 1, u64> negate_b;
|
|
BitField<46, 1, u64> abs_a;
|
|
BitField<48, 1, u64> negate_a;
|
|
BitField<49, 1, u64> abs_b;
|
|
BitField<50, 1, u64> saturate_d;
|
|
BitField<56, 1, u64> negate_imm;
|
|
|
|
union {
|
|
BitField<39, 3, u64> pred;
|
|
BitField<42, 1, u64> negate_pred;
|
|
} fmnmx;
|
|
|
|
union {
|
|
BitField<39, 1, u64> invert_a;
|
|
BitField<40, 1, u64> invert_b;
|
|
BitField<41, 2, LogicOperation> operation;
|
|
BitField<44, 2, PredicateResultMode> pred_result_mode;
|
|
BitField<48, 3, Pred> pred48;
|
|
} lop;
|
|
|
|
union {
|
|
BitField<53, 2, LogicOperation> operation;
|
|
BitField<55, 1, u64> invert_a;
|
|
BitField<56, 1, u64> invert_b;
|
|
} lop32i;
|
|
|
|
union {
|
|
BitField<28, 8, u64> imm_lut28;
|
|
BitField<48, 8, u64> imm_lut48;
|
|
|
|
u32 GetImmLut28() const {
|
|
return static_cast<u32>(imm_lut28);
|
|
}
|
|
|
|
u32 GetImmLut48() const {
|
|
return static_cast<u32>(imm_lut48);
|
|
}
|
|
} lop3;
|
|
|
|
u16 GetImm20_16() const {
|
|
return static_cast<u16>(imm20_16);
|
|
}
|
|
|
|
u32 GetImm20_19() const {
|
|
u32 imm{static_cast<u32>(imm20_19)};
|
|
imm <<= 12;
|
|
imm |= negate_imm ? 0x80000000 : 0;
|
|
return imm;
|
|
}
|
|
|
|
u32 GetImm20_32() const {
|
|
return static_cast<u32>(imm20_32);
|
|
}
|
|
|
|
s32 GetSignedImm20_20() const {
|
|
u32 immediate = static_cast<u32>(imm20_19 | (negate_imm << 19));
|
|
// Sign extend the 20-bit value.
|
|
u32 mask = 1U << (20 - 1);
|
|
return static_cast<s32>((immediate ^ mask) - mask);
|
|
}
|
|
} alu;
|
|
|
|
union {
|
|
BitField<38, 1, u64> idx;
|
|
BitField<51, 1, u64> saturate;
|
|
BitField<52, 2, IpaSampleMode> sample_mode;
|
|
BitField<54, 2, IpaInterpMode> interp_mode;
|
|
} ipa;
|
|
|
|
union {
|
|
BitField<39, 2, u64> tab5cb8_2;
|
|
BitField<41, 3, u64> postfactor;
|
|
BitField<44, 2, u64> tab5c68_0;
|
|
BitField<48, 1, u64> negate_b;
|
|
} fmul;
|
|
|
|
union {
|
|
BitField<55, 1, u64> saturate;
|
|
} fmul32;
|
|
|
|
union {
|
|
BitField<52, 1, u64> generates_cc;
|
|
} op_32;
|
|
|
|
union {
|
|
BitField<48, 1, u64> is_signed;
|
|
} shift;
|
|
|
|
union {
|
|
BitField<39, 5, u64> shift_amount;
|
|
BitField<48, 1, u64> negate_b;
|
|
BitField<49, 1, u64> negate_a;
|
|
} alu_integer;
|
|
|
|
union {
|
|
BitField<39, 1, u64> ftz;
|
|
BitField<32, 1, u64> saturate;
|
|
BitField<49, 2, HalfMerge> merge;
|
|
|
|
BitField<43, 1, u64> negate_a;
|
|
BitField<44, 1, u64> abs_a;
|
|
BitField<47, 2, HalfType> type_a;
|
|
|
|
BitField<31, 1, u64> negate_b;
|
|
BitField<30, 1, u64> abs_b;
|
|
BitField<28, 2, HalfType> type_b;
|
|
|
|
BitField<35, 2, HalfType> type_c;
|
|
} alu_half;
|
|
|
|
union {
|
|
BitField<39, 2, HalfPrecision> precision;
|
|
BitField<39, 1, u64> ftz;
|
|
BitField<52, 1, u64> saturate;
|
|
BitField<49, 2, HalfMerge> merge;
|
|
|
|
BitField<43, 1, u64> negate_a;
|
|
BitField<44, 1, u64> abs_a;
|
|
BitField<47, 2, HalfType> type_a;
|
|
} alu_half_imm;
|
|
|
|
union {
|
|
BitField<29, 1, u64> first_negate;
|
|
BitField<20, 9, u64> first;
|
|
|
|
BitField<56, 1, u64> second_negate;
|
|
BitField<30, 9, u64> second;
|
|
|
|
u32 PackImmediates() const {
|
|
// Immediates are half floats shifted.
|
|
constexpr u32 imm_shift = 6;
|
|
return static_cast<u32>((first << imm_shift) | (second << (16 + imm_shift)));
|
|
}
|
|
} half_imm;
|
|
|
|
union {
|
|
union {
|
|
BitField<37, 2, HalfPrecision> precision;
|
|
BitField<32, 1, u64> saturate;
|
|
|
|
BitField<31, 1, u64> negate_b;
|
|
BitField<30, 1, u64> negate_c;
|
|
BitField<35, 2, HalfType> type_c;
|
|
} rr;
|
|
|
|
BitField<57, 2, HalfPrecision> precision;
|
|
BitField<52, 1, u64> saturate;
|
|
|
|
BitField<49, 2, HalfMerge> merge;
|
|
|
|
BitField<47, 2, HalfType> type_a;
|
|
|
|
BitField<56, 1, u64> negate_b;
|
|
BitField<28, 2, HalfType> type_b;
|
|
|
|
BitField<51, 1, u64> negate_c;
|
|
BitField<53, 2, HalfType> type_reg39;
|
|
} hfma2;
|
|
|
|
union {
|
|
BitField<40, 1, u64> invert;
|
|
} popc;
|
|
|
|
union {
|
|
BitField<39, 3, u64> pred;
|
|
BitField<42, 1, u64> neg_pred;
|
|
} sel;
|
|
|
|
union {
|
|
BitField<39, 3, u64> pred;
|
|
BitField<42, 1, u64> negate_pred;
|
|
BitField<43, 2, IMinMaxExchange> exchange;
|
|
BitField<48, 1, u64> is_signed;
|
|
} imnmx;
|
|
|
|
union {
|
|
BitField<31, 2, IAdd3Height> height_c;
|
|
BitField<33, 2, IAdd3Height> height_b;
|
|
BitField<35, 2, IAdd3Height> height_a;
|
|
BitField<37, 2, IAdd3Mode> mode;
|
|
BitField<49, 1, u64> neg_c;
|
|
BitField<50, 1, u64> neg_b;
|
|
BitField<51, 1, u64> neg_a;
|
|
} iadd3;
|
|
|
|
union {
|
|
BitField<54, 1, u64> saturate;
|
|
BitField<56, 1, u64> negate_a;
|
|
} iadd32i;
|
|
|
|
union {
|
|
BitField<53, 1, u64> negate_b;
|
|
BitField<54, 1, u64> abs_a;
|
|
BitField<56, 1, u64> negate_a;
|
|
BitField<57, 1, u64> abs_b;
|
|
} fadd32i;
|
|
|
|
union {
|
|
BitField<20, 8, u64> shift_position;
|
|
BitField<28, 8, u64> shift_length;
|
|
BitField<48, 1, u64> negate_b;
|
|
BitField<49, 1, u64> negate_a;
|
|
|
|
u64 GetLeftShiftValue() const {
|
|
return 32 - (shift_position + shift_length);
|
|
}
|
|
} bfe;
|
|
|
|
union {
|
|
BitField<48, 3, u64> pred48;
|
|
|
|
union {
|
|
BitField<20, 20, u64> entry_a;
|
|
BitField<39, 5, u64> entry_b;
|
|
BitField<45, 1, u64> neg;
|
|
BitField<46, 1, u64> uses_cc;
|
|
} imm;
|
|
|
|
union {
|
|
BitField<20, 14, u64> cb_index;
|
|
BitField<34, 5, u64> cb_offset;
|
|
BitField<56, 1, u64> neg;
|
|
BitField<57, 1, u64> uses_cc;
|
|
} hi;
|
|
|
|
union {
|
|
BitField<20, 14, u64> cb_index;
|
|
BitField<34, 5, u64> cb_offset;
|
|
BitField<39, 5, u64> entry_a;
|
|
BitField<45, 1, u64> neg;
|
|
BitField<46, 1, u64> uses_cc;
|
|
} rz;
|
|
|
|
union {
|
|
BitField<39, 5, u64> entry_a;
|
|
BitField<45, 1, u64> neg;
|
|
BitField<46, 1, u64> uses_cc;
|
|
} r1;
|
|
|
|
union {
|
|
BitField<28, 8, u64> entry_a;
|
|
BitField<37, 1, u64> neg;
|
|
BitField<38, 1, u64> uses_cc;
|
|
} r2;
|
|
|
|
} lea;
|
|
|
|
union {
|
|
BitField<0, 5, FlowCondition> cond;
|
|
} flow;
|
|
|
|
union {
|
|
BitField<47, 1, u64> cc;
|
|
BitField<48, 1, u64> negate_b;
|
|
BitField<49, 1, u64> negate_c;
|
|
BitField<51, 2, u64> tab5980_1;
|
|
BitField<53, 2, u64> tab5980_0;
|
|
} ffma;
|
|
|
|
union {
|
|
BitField<48, 3, UniformType> type;
|
|
BitField<44, 2, u64> unknown;
|
|
} ld_c;
|
|
|
|
union {
|
|
BitField<48, 3, StoreType> type;
|
|
} ldst_sl;
|
|
|
|
union {
|
|
BitField<44, 2, u64> unknown;
|
|
} ld_l;
|
|
|
|
union {
|
|
BitField<44, 2, StoreCacheManagement> cache_management;
|
|
} st_l;
|
|
|
|
union {
|
|
BitField<48, 3, UniformType> type;
|
|
BitField<46, 2, u64> cache_mode;
|
|
} ldg;
|
|
|
|
union {
|
|
BitField<48, 3, UniformType> type;
|
|
BitField<46, 2, u64> cache_mode;
|
|
} stg;
|
|
|
|
union {
|
|
BitField<32, 1, PhysicalAttributeDirection> direction;
|
|
BitField<47, 3, AttributeSize> size;
|
|
BitField<20, 11, u64> address;
|
|
} al2p;
|
|
|
|
union {
|
|
BitField<53, 3, UniformType> type;
|
|
BitField<52, 1, u64> extended;
|
|
} generic;
|
|
|
|
union {
|
|
BitField<0, 3, u64> pred0;
|
|
BitField<3, 3, u64> pred3;
|
|
BitField<7, 1, u64> abs_a;
|
|
BitField<39, 3, u64> pred39;
|
|
BitField<42, 1, u64> neg_pred;
|
|
BitField<43, 1, u64> neg_a;
|
|
BitField<44, 1, u64> abs_b;
|
|
BitField<45, 2, PredOperation> op;
|
|
BitField<47, 1, u64> ftz;
|
|
BitField<48, 4, PredCondition> cond;
|
|
} fsetp;
|
|
|
|
union {
|
|
BitField<0, 3, u64> pred0;
|
|
BitField<3, 3, u64> pred3;
|
|
BitField<39, 3, u64> pred39;
|
|
BitField<42, 1, u64> neg_pred;
|
|
BitField<45, 2, PredOperation> op;
|
|
BitField<48, 1, u64> is_signed;
|
|
BitField<49, 3, PredCondition> cond;
|
|
} isetp;
|
|
|
|
union {
|
|
BitField<0, 3, u64> pred0;
|
|
BitField<3, 3, u64> pred3;
|
|
BitField<12, 3, u64> pred12;
|
|
BitField<15, 1, u64> neg_pred12;
|
|
BitField<24, 2, PredOperation> cond;
|
|
BitField<29, 3, u64> pred29;
|
|
BitField<32, 1, u64> neg_pred29;
|
|
BitField<39, 3, u64> pred39;
|
|
BitField<42, 1, u64> neg_pred39;
|
|
BitField<45, 2, PredOperation> op;
|
|
} psetp;
|
|
|
|
union {
|
|
BitField<43, 4, PredCondition> cond;
|
|
BitField<45, 2, PredOperation> op;
|
|
BitField<3, 3, u64> pred3;
|
|
BitField<0, 3, u64> pred0;
|
|
BitField<39, 3, u64> pred39;
|
|
} vsetp;
|
|
|
|
union {
|
|
BitField<12, 3, u64> pred12;
|
|
BitField<15, 1, u64> neg_pred12;
|
|
BitField<24, 2, PredOperation> cond;
|
|
BitField<29, 3, u64> pred29;
|
|
BitField<32, 1, u64> neg_pred29;
|
|
BitField<39, 3, u64> pred39;
|
|
BitField<42, 1, u64> neg_pred39;
|
|
BitField<44, 1, u64> bf;
|
|
BitField<45, 2, PredOperation> op;
|
|
} pset;
|
|
|
|
union {
|
|
BitField<0, 3, u64> pred0;
|
|
BitField<3, 3, u64> pred3;
|
|
BitField<8, 5, ConditionCode> cc; // flag in cc
|
|
BitField<39, 3, u64> pred39;
|
|
BitField<42, 1, u64> neg_pred39;
|
|
BitField<45, 4, PredOperation> op; // op with pred39
|
|
} csetp;
|
|
|
|
union {
|
|
BitField<6, 1, u64> ftz;
|
|
BitField<45, 2, PredOperation> op;
|
|
BitField<3, 3, u64> pred3;
|
|
BitField<0, 3, u64> pred0;
|
|
BitField<43, 1, u64> negate_a;
|
|
BitField<44, 1, u64> abs_a;
|
|
BitField<47, 2, HalfType> type_a;
|
|
union {
|
|
BitField<35, 4, PredCondition> cond;
|
|
BitField<49, 1, u64> h_and;
|
|
BitField<31, 1, u64> negate_b;
|
|
BitField<30, 1, u64> abs_b;
|
|
BitField<28, 2, HalfType> type_b;
|
|
} reg;
|
|
union {
|
|
BitField<56, 1, u64> negate_b;
|
|
BitField<54, 1, u64> abs_b;
|
|
} cbuf;
|
|
union {
|
|
BitField<49, 4, PredCondition> cond;
|
|
BitField<53, 1, u64> h_and;
|
|
} cbuf_and_imm;
|
|
BitField<42, 1, u64> neg_pred;
|
|
BitField<39, 3, u64> pred39;
|
|
} hsetp2;
|
|
|
|
union {
|
|
BitField<40, 1, R2pMode> mode;
|
|
BitField<41, 2, u64> byte;
|
|
BitField<20, 7, u64> immediate_mask;
|
|
} r2p;
|
|
|
|
union {
|
|
BitField<39, 3, u64> pred39;
|
|
BitField<42, 1, u64> neg_pred;
|
|
BitField<43, 1, u64> neg_a;
|
|
BitField<44, 1, u64> abs_b;
|
|
BitField<45, 2, PredOperation> op;
|
|
BitField<48, 4, PredCondition> cond;
|
|
BitField<52, 1, u64> bf;
|
|
BitField<53, 1, u64> neg_b;
|
|
BitField<54, 1, u64> abs_a;
|
|
BitField<55, 1, u64> ftz;
|
|
} fset;
|
|
|
|
union {
|
|
BitField<49, 1, u64> bf;
|
|
BitField<35, 3, PredCondition> cond;
|
|
BitField<50, 1, u64> ftz;
|
|
BitField<45, 2, PredOperation> op;
|
|
BitField<43, 1, u64> negate_a;
|
|
BitField<44, 1, u64> abs_a;
|
|
BitField<47, 2, HalfType> type_a;
|
|
BitField<31, 1, u64> negate_b;
|
|
BitField<30, 1, u64> abs_b;
|
|
BitField<28, 2, HalfType> type_b;
|
|
BitField<42, 1, u64> neg_pred;
|
|
BitField<39, 3, u64> pred39;
|
|
} hset2;
|
|
|
|
union {
|
|
BitField<39, 3, u64> pred39;
|
|
BitField<42, 1, u64> neg_pred;
|
|
BitField<44, 1, u64> bf;
|
|
BitField<45, 2, PredOperation> op;
|
|
BitField<48, 1, u64> is_signed;
|
|
BitField<49, 3, PredCondition> cond;
|
|
} iset;
|
|
|
|
union {
|
|
BitField<41, 2, u64> selector; // i2i and i2f only
|
|
BitField<45, 1, u64> negate_a;
|
|
BitField<49, 1, u64> abs_a;
|
|
BitField<10, 2, Register::Size> src_size;
|
|
BitField<13, 1, u64> is_input_signed;
|
|
BitField<8, 2, Register::Size> dst_size;
|
|
BitField<12, 1, u64> is_output_signed;
|
|
|
|
union {
|
|
BitField<39, 2, u64> tab5cb8_2;
|
|
} i2f;
|
|
|
|
union {
|
|
BitField<39, 2, F2iRoundingOp> rounding;
|
|
} f2i;
|
|
|
|
union {
|
|
BitField<39, 4, u64> rounding;
|
|
// H0, H1 extract for F16 missing
|
|
BitField<41, 1, u64> selector; // Guessed as some games set it, TODO: reverse this value
|
|
F2fRoundingOp GetRoundingMode() const {
|
|
constexpr u64 rounding_mask = 0x0B;
|
|
return static_cast<F2fRoundingOp>(rounding.Value() & rounding_mask);
|
|
}
|
|
} f2f;
|
|
|
|
} conversion;
|
|
|
|
union {
|
|
BitField<28, 1, u64> array;
|
|
BitField<29, 2, TextureType> texture_type;
|
|
BitField<31, 4, u64> component_mask;
|
|
BitField<49, 1, u64> nodep_flag;
|
|
BitField<50, 1, u64> dc_flag;
|
|
BitField<54, 1, u64> aoffi_flag;
|
|
BitField<55, 3, TextureProcessMode> process_mode;
|
|
|
|
bool IsComponentEnabled(std::size_t component) const {
|
|
return ((1ull << component) & component_mask) != 0;
|
|
}
|
|
|
|
TextureProcessMode GetTextureProcessMode() const {
|
|
return process_mode;
|
|
}
|
|
|
|
bool UsesMiscMode(TextureMiscMode mode) const {
|
|
switch (mode) {
|
|
case TextureMiscMode::DC:
|
|
return dc_flag != 0;
|
|
case TextureMiscMode::NODEP:
|
|
return nodep_flag != 0;
|
|
case TextureMiscMode::AOFFI:
|
|
return aoffi_flag != 0;
|
|
default:
|
|
break;
|
|
}
|
|
return false;
|
|
}
|
|
} tex;
|
|
|
|
union {
|
|
BitField<28, 1, u64> array;
|
|
BitField<29, 2, TextureType> texture_type;
|
|
BitField<31, 4, u64> component_mask;
|
|
BitField<49, 1, u64> nodep_flag;
|
|
BitField<50, 1, u64> dc_flag;
|
|
BitField<36, 1, u64> aoffi_flag;
|
|
BitField<37, 3, TextureProcessMode> process_mode;
|
|
|
|
bool IsComponentEnabled(std::size_t component) const {
|
|
return ((1ULL << component) & component_mask) != 0;
|
|
}
|
|
|
|
TextureProcessMode GetTextureProcessMode() const {
|
|
return process_mode;
|
|
}
|
|
|
|
bool UsesMiscMode(TextureMiscMode mode) const {
|
|
switch (mode) {
|
|
case TextureMiscMode::DC:
|
|
return dc_flag != 0;
|
|
case TextureMiscMode::NODEP:
|
|
return nodep_flag != 0;
|
|
case TextureMiscMode::AOFFI:
|
|
return aoffi_flag != 0;
|
|
default:
|
|
break;
|
|
}
|
|
return false;
|
|
}
|
|
} tex_b;
|
|
|
|
union {
|
|
BitField<22, 6, TextureQueryType> query_type;
|
|
BitField<31, 4, u64> component_mask;
|
|
BitField<49, 1, u64> nodep_flag;
|
|
|
|
bool UsesMiscMode(TextureMiscMode mode) const {
|
|
switch (mode) {
|
|
case TextureMiscMode::NODEP:
|
|
return nodep_flag != 0;
|
|
default:
|
|
break;
|
|
}
|
|
return false;
|
|
}
|
|
|
|
bool IsComponentEnabled(std::size_t component) const {
|
|
return ((1ULL << component) & component_mask) != 0;
|
|
}
|
|
} txq;
|
|
|
|
union {
|
|
BitField<28, 1, u64> array;
|
|
BitField<29, 2, TextureType> texture_type;
|
|
BitField<31, 4, u64> component_mask;
|
|
BitField<35, 1, u64> ndv_flag;
|
|
BitField<49, 1, u64> nodep_flag;
|
|
|
|
bool IsComponentEnabled(std::size_t component) const {
|
|
return ((1ull << component) & component_mask) != 0;
|
|
}
|
|
|
|
bool UsesMiscMode(TextureMiscMode mode) const {
|
|
switch (mode) {
|
|
case TextureMiscMode::NDV:
|
|
return (ndv_flag != 0);
|
|
case TextureMiscMode::NODEP:
|
|
return (nodep_flag != 0);
|
|
default:
|
|
break;
|
|
}
|
|
return false;
|
|
}
|
|
} tmml;
|
|
|
|
union {
|
|
BitField<28, 1, u64> array;
|
|
BitField<29, 2, TextureType> texture_type;
|
|
BitField<35, 1, u64> ndv_flag;
|
|
BitField<49, 1, u64> nodep_flag;
|
|
BitField<50, 1, u64> dc_flag;
|
|
BitField<54, 2, u64> info;
|
|
BitField<56, 2, u64> component;
|
|
|
|
bool UsesMiscMode(TextureMiscMode mode) const {
|
|
switch (mode) {
|
|
case TextureMiscMode::NDV:
|
|
return ndv_flag != 0;
|
|
case TextureMiscMode::NODEP:
|
|
return nodep_flag != 0;
|
|
case TextureMiscMode::DC:
|
|
return dc_flag != 0;
|
|
case TextureMiscMode::AOFFI:
|
|
return info == 1;
|
|
case TextureMiscMode::PTP:
|
|
return info == 2;
|
|
default:
|
|
break;
|
|
}
|
|
return false;
|
|
}
|
|
} tld4;
|
|
|
|
union {
|
|
BitField<49, 1, u64> nodep_flag;
|
|
BitField<50, 1, u64> dc_flag;
|
|
BitField<51, 1, u64> aoffi_flag;
|
|
BitField<52, 2, u64> component;
|
|
|
|
bool UsesMiscMode(TextureMiscMode mode) const {
|
|
switch (mode) {
|
|
case TextureMiscMode::DC:
|
|
return dc_flag != 0;
|
|
case TextureMiscMode::NODEP:
|
|
return nodep_flag != 0;
|
|
case TextureMiscMode::AOFFI:
|
|
return aoffi_flag != 0;
|
|
default:
|
|
break;
|
|
}
|
|
return false;
|
|
}
|
|
} tld4s;
|
|
|
|
union {
|
|
BitField<0, 8, Register> gpr0;
|
|
BitField<28, 8, Register> gpr28;
|
|
BitField<49, 1, u64> nodep_flag;
|
|
BitField<50, 3, u64> component_mask_selector;
|
|
BitField<53, 4, u64> texture_info;
|
|
BitField<59, 1, u64> fp32_flag;
|
|
|
|
TextureType GetTextureType() const {
|
|
// The TEXS instruction has a weird encoding for the texture type.
|
|
if (texture_info == 0)
|
|
return TextureType::Texture1D;
|
|
if (texture_info >= 1 && texture_info <= 9)
|
|
return TextureType::Texture2D;
|
|
if (texture_info >= 10 && texture_info <= 11)
|
|
return TextureType::Texture3D;
|
|
if (texture_info >= 12 && texture_info <= 13)
|
|
return TextureType::TextureCube;
|
|
|
|
LOG_CRITICAL(HW_GPU, "Unhandled texture_info: {}",
|
|
static_cast<u32>(texture_info.Value()));
|
|
UNREACHABLE();
|
|
return TextureType::Texture1D;
|
|
}
|
|
|
|
TextureProcessMode GetTextureProcessMode() const {
|
|
switch (texture_info) {
|
|
case 0:
|
|
case 2:
|
|
case 6:
|
|
case 8:
|
|
case 9:
|
|
case 11:
|
|
return TextureProcessMode::LZ;
|
|
case 3:
|
|
case 5:
|
|
case 13:
|
|
return TextureProcessMode::LL;
|
|
default:
|
|
break;
|
|
}
|
|
return TextureProcessMode::None;
|
|
}
|
|
|
|
bool UsesMiscMode(TextureMiscMode mode) const {
|
|
switch (mode) {
|
|
case TextureMiscMode::DC:
|
|
return (texture_info >= 4 && texture_info <= 6) || texture_info == 9;
|
|
case TextureMiscMode::NODEP:
|
|
return nodep_flag != 0;
|
|
default:
|
|
break;
|
|
}
|
|
return false;
|
|
}
|
|
|
|
bool IsArrayTexture() const {
|
|
// TEXS only supports Texture2D arrays.
|
|
return texture_info >= 7 && texture_info <= 9;
|
|
}
|
|
|
|
bool HasTwoDestinations() const {
|
|
return gpr28.Value() != Register::ZeroIndex;
|
|
}
|
|
|
|
bool IsComponentEnabled(std::size_t component) const {
|
|
static constexpr std::array<std::array<u32, 8>, 4> mask_lut{{
|
|
{},
|
|
{0x1, 0x2, 0x4, 0x8, 0x3, 0x9, 0xa, 0xc},
|
|
{0x1, 0x2, 0x4, 0x8, 0x3, 0x9, 0xa, 0xc},
|
|
{0x7, 0xb, 0xd, 0xe, 0xf},
|
|
}};
|
|
|
|
std::size_t index{gpr0.Value() != Register::ZeroIndex ? 1U : 0U};
|
|
index |= gpr28.Value() != Register::ZeroIndex ? 2 : 0;
|
|
|
|
u32 mask = mask_lut[index][component_mask_selector];
|
|
// A mask of 0 means this instruction uses an unimplemented mask.
|
|
ASSERT(mask != 0);
|
|
return ((1ull << component) & mask) != 0;
|
|
}
|
|
} texs;
|
|
|
|
union {
|
|
BitField<28, 1, u64> is_array;
|
|
BitField<29, 2, TextureType> texture_type;
|
|
BitField<35, 1, u64> aoffi;
|
|
BitField<49, 1, u64> nodep_flag;
|
|
BitField<50, 1, u64> ms; // Multisample?
|
|
BitField<54, 1, u64> cl;
|
|
BitField<55, 1, u64> process_mode;
|
|
|
|
TextureProcessMode GetTextureProcessMode() const {
|
|
return process_mode == 0 ? TextureProcessMode::LZ : TextureProcessMode::LL;
|
|
}
|
|
} tld;
|
|
|
|
union {
|
|
BitField<49, 1, u64> nodep_flag;
|
|
BitField<53, 4, u64> texture_info;
|
|
BitField<59, 1, u64> fp32_flag;
|
|
|
|
TextureType GetTextureType() const {
|
|
// The TLDS instruction has a weird encoding for the texture type.
|
|
if (texture_info >= 0 && texture_info <= 1) {
|
|
return TextureType::Texture1D;
|
|
}
|
|
if (texture_info == 2 || texture_info == 8 || texture_info == 12 ||
|
|
(texture_info >= 4 && texture_info <= 6)) {
|
|
return TextureType::Texture2D;
|
|
}
|
|
if (texture_info == 7) {
|
|
return TextureType::Texture3D;
|
|
}
|
|
|
|
LOG_CRITICAL(HW_GPU, "Unhandled texture_info: {}",
|
|
static_cast<u32>(texture_info.Value()));
|
|
UNREACHABLE();
|
|
return TextureType::Texture1D;
|
|
}
|
|
|
|
TextureProcessMode GetTextureProcessMode() const {
|
|
if (texture_info == 1 || texture_info == 5 || texture_info == 12)
|
|
return TextureProcessMode::LL;
|
|
return TextureProcessMode::LZ;
|
|
}
|
|
|
|
bool UsesMiscMode(TextureMiscMode mode) const {
|
|
switch (mode) {
|
|
case TextureMiscMode::AOFFI:
|
|
return texture_info == 12 || texture_info == 4;
|
|
case TextureMiscMode::MZ:
|
|
return texture_info == 5;
|
|
case TextureMiscMode::NODEP:
|
|
return nodep_flag != 0;
|
|
default:
|
|
break;
|
|
}
|
|
return false;
|
|
}
|
|
|
|
bool IsArrayTexture() const {
|
|
// TEXS only supports Texture2D arrays.
|
|
return texture_info == 8;
|
|
}
|
|
} tlds;
|
|
|
|
union {
|
|
BitField<24, 2, StoreCacheManagement> cache_management;
|
|
BitField<33, 3, ImageType> image_type;
|
|
BitField<49, 2, OutOfBoundsStore> out_of_bounds_store;
|
|
BitField<51, 1, u64> is_immediate;
|
|
BitField<52, 1, SurfaceDataMode> mode;
|
|
|
|
BitField<20, 3, StoreType> store_data_layout;
|
|
BitField<20, 4, u64> component_mask_selector;
|
|
|
|
bool IsComponentEnabled(std::size_t component) const {
|
|
ASSERT(mode == SurfaceDataMode::P);
|
|
constexpr u8 R = 0b0001;
|
|
constexpr u8 G = 0b0010;
|
|
constexpr u8 B = 0b0100;
|
|
constexpr u8 A = 0b1000;
|
|
constexpr std::array<u8, 16> mask = {
|
|
0, (R), (G), (R | G), (B), (R | B),
|
|
(G | B), (R | G | B), (A), (R | A), (G | A), (R | G | A),
|
|
(B | A), (R | B | A), (G | B | A), (R | G | B | A)};
|
|
return std::bitset<4>{mask.at(component_mask_selector)}.test(component);
|
|
}
|
|
|
|
StoreType GetStoreDataLayout() const {
|
|
ASSERT(mode == SurfaceDataMode::D_BA);
|
|
return store_data_layout;
|
|
}
|
|
} sust;
|
|
|
|
union {
|
|
BitField<20, 24, u64> target;
|
|
BitField<5, 1, u64> constant_buffer;
|
|
|
|
s32 GetBranchTarget() const {
|
|
// Sign extend the branch target offset
|
|
u32 mask = 1U << (24 - 1);
|
|
u32 value = static_cast<u32>(target);
|
|
// The branch offset is relative to the next instruction and is stored in bytes, so
|
|
// divide it by the size of an instruction and add 1 to it.
|
|
return static_cast<s32>((value ^ mask) - mask) / sizeof(Instruction) + 1;
|
|
}
|
|
} bra;
|
|
|
|
union {
|
|
BitField<20, 24, u64> target;
|
|
BitField<5, 1, u64> constant_buffer;
|
|
|
|
s32 GetBranchExtend() const {
|
|
// Sign extend the branch target offset
|
|
u32 mask = 1U << (24 - 1);
|
|
u32 value = static_cast<u32>(target);
|
|
// The branch offset is relative to the next instruction and is stored in bytes, so
|
|
// divide it by the size of an instruction and add 1 to it.
|
|
return static_cast<s32>((value ^ mask) - mask) / sizeof(Instruction) + 1;
|
|
}
|
|
} brx;
|
|
|
|
union {
|
|
BitField<39, 1, u64> emit; // EmitVertex
|
|
BitField<40, 1, u64> cut; // EndPrimitive
|
|
} out;
|
|
|
|
union {
|
|
BitField<31, 1, u64> skew;
|
|
BitField<32, 1, u64> o;
|
|
BitField<33, 2, IsberdMode> mode;
|
|
BitField<47, 2, IsberdShift> shift;
|
|
} isberd;
|
|
|
|
union {
|
|
BitField<48, 1, u64> signed_a;
|
|
BitField<38, 1, u64> is_byte_chunk_a;
|
|
BitField<36, 2, VideoType> type_a;
|
|
BitField<36, 2, u64> byte_height_a;
|
|
|
|
BitField<49, 1, u64> signed_b;
|
|
BitField<50, 1, u64> use_register_b;
|
|
BitField<30, 1, u64> is_byte_chunk_b;
|
|
BitField<28, 2, VideoType> type_b;
|
|
BitField<28, 2, u64> byte_height_b;
|
|
} video;
|
|
|
|
union {
|
|
BitField<51, 2, VmadShr> shr;
|
|
BitField<55, 1, u64> saturate; // Saturates the result (a * b + c)
|
|
BitField<47, 1, u64> cc;
|
|
} vmad;
|
|
|
|
union {
|
|
BitField<20, 16, u64> imm20_16;
|
|
BitField<35, 1, u64> high_b_rr; // used on RR
|
|
BitField<36, 1, u64> product_shift_left;
|
|
BitField<37, 1, u64> merge_37;
|
|
BitField<48, 1, u64> sign_a;
|
|
BitField<49, 1, u64> sign_b;
|
|
BitField<50, 2, XmadMode> mode_cbf; // used by CR, RC
|
|
BitField<50, 3, XmadMode> mode;
|
|
BitField<52, 1, u64> high_b;
|
|
BitField<53, 1, u64> high_a;
|
|
BitField<55, 1, u64> product_shift_left_second; // used on CR
|
|
BitField<56, 1, u64> merge_56;
|
|
} xmad;
|
|
|
|
union {
|
|
BitField<20, 14, u64> offset;
|
|
BitField<34, 5, u64> index;
|
|
|
|
u64 GetOffset() const {
|
|
return offset * 4;
|
|
}
|
|
} cbuf34;
|
|
|
|
union {
|
|
BitField<20, 16, s64> offset;
|
|
BitField<36, 5, u64> index;
|
|
|
|
s64 GetOffset() const {
|
|
return offset;
|
|
}
|
|
} cbuf36;
|
|
|
|
// Unsure about the size of this one.
|
|
// It's always used with a gpr0, so any size should be fine.
|
|
BitField<20, 8, SystemVariable> sys20;
|
|
|
|
BitField<47, 1, u64> generates_cc;
|
|
BitField<61, 1, u64> is_b_imm;
|
|
BitField<60, 1, u64> is_b_gpr;
|
|
BitField<59, 1, u64> is_c_gpr;
|
|
BitField<20, 24, s64> smem_imm;
|
|
BitField<0, 5, ConditionCode> flow_condition_code;
|
|
|
|
Attribute attribute;
|
|
Sampler sampler;
|
|
Image image;
|
|
|
|
u64 value;
|
|
};
|
|
static_assert(sizeof(Instruction) == 0x8, "Incorrect structure size");
|
|
static_assert(std::is_standard_layout_v<Instruction>, "Instruction is not standard layout");
|
|
|
|
class OpCode {
|
|
public:
|
|
enum class Id {
|
|
KIL,
|
|
SSY,
|
|
SYNC,
|
|
BRK,
|
|
DEPBAR,
|
|
VOTE,
|
|
BFE_C,
|
|
BFE_R,
|
|
BFE_IMM,
|
|
BFI_IMM_R,
|
|
BRA,
|
|
BRX,
|
|
PBK,
|
|
LD_A,
|
|
LD_L,
|
|
LD_S,
|
|
LD_C,
|
|
LD, // Load from generic memory
|
|
LDG, // Load from global memory
|
|
ST_A,
|
|
ST_L,
|
|
ST_S,
|
|
ST, // Store in generic memory
|
|
STG, // Store in global memory
|
|
AL2P, // Transforms attribute memory into physical memory
|
|
TEX,
|
|
TEX_B, // Texture Load Bindless
|
|
TXQ, // Texture Query
|
|
TXQ_B, // Texture Query Bindless
|
|
TEXS, // Texture Fetch with scalar/non-vec4 source/destinations
|
|
TLD, // Texture Load
|
|
TLDS, // Texture Load with scalar/non-vec4 source/destinations
|
|
TLD4, // Texture Load 4
|
|
TLD4S, // Texture Load 4 with scalar / non - vec4 source / destinations
|
|
TMML_B, // Texture Mip Map Level
|
|
TMML, // Texture Mip Map Level
|
|
SUST, // Surface Store
|
|
EXIT,
|
|
NOP,
|
|
IPA,
|
|
OUT_R, // Emit vertex/primitive
|
|
ISBERD,
|
|
VMAD,
|
|
VSETP,
|
|
FFMA_IMM, // Fused Multiply and Add
|
|
FFMA_CR,
|
|
FFMA_RC,
|
|
FFMA_RR,
|
|
FADD_C,
|
|
FADD_R,
|
|
FADD_IMM,
|
|
FADD32I,
|
|
FMUL_C,
|
|
FMUL_R,
|
|
FMUL_IMM,
|
|
FMUL32_IMM,
|
|
IADD_C,
|
|
IADD_R,
|
|
IADD_IMM,
|
|
IADD3_C, // Add 3 Integers
|
|
IADD3_R,
|
|
IADD3_IMM,
|
|
IADD32I,
|
|
ISCADD_C, // Scale and Add
|
|
ISCADD_R,
|
|
ISCADD_IMM,
|
|
LEA_R1,
|
|
LEA_R2,
|
|
LEA_RZ,
|
|
LEA_IMM,
|
|
LEA_HI,
|
|
HADD2_C,
|
|
HADD2_R,
|
|
HADD2_IMM,
|
|
HMUL2_C,
|
|
HMUL2_R,
|
|
HMUL2_IMM,
|
|
HFMA2_CR,
|
|
HFMA2_RC,
|
|
HFMA2_RR,
|
|
HFMA2_IMM_R,
|
|
HSETP2_C,
|
|
HSETP2_R,
|
|
HSETP2_IMM,
|
|
HSET2_R,
|
|
POPC_C,
|
|
POPC_R,
|
|
POPC_IMM,
|
|
SEL_C,
|
|
SEL_R,
|
|
SEL_IMM,
|
|
MUFU, // Multi-Function Operator
|
|
RRO_C, // Range Reduction Operator
|
|
RRO_R,
|
|
RRO_IMM,
|
|
F2F_C,
|
|
F2F_R,
|
|
F2F_IMM,
|
|
F2I_C,
|
|
F2I_R,
|
|
F2I_IMM,
|
|
I2F_C,
|
|
I2F_R,
|
|
I2F_IMM,
|
|
I2I_C,
|
|
I2I_R,
|
|
I2I_IMM,
|
|
LOP_C,
|
|
LOP_R,
|
|
LOP_IMM,
|
|
LOP32I,
|
|
LOP3_C,
|
|
LOP3_R,
|
|
LOP3_IMM,
|
|
MOV_C,
|
|
MOV_R,
|
|
MOV_IMM,
|
|
MOV_SYS,
|
|
MOV32_IMM,
|
|
SHL_C,
|
|
SHL_R,
|
|
SHL_IMM,
|
|
SHR_C,
|
|
SHR_R,
|
|
SHR_IMM,
|
|
FMNMX_C,
|
|
FMNMX_R,
|
|
FMNMX_IMM,
|
|
IMNMX_C,
|
|
IMNMX_R,
|
|
IMNMX_IMM,
|
|
FSETP_C, // Set Predicate
|
|
FSETP_R,
|
|
FSETP_IMM,
|
|
FSET_C,
|
|
FSET_R,
|
|
FSET_IMM,
|
|
ISETP_C,
|
|
ISETP_IMM,
|
|
ISETP_R,
|
|
ISET_R,
|
|
ISET_C,
|
|
ISET_IMM,
|
|
PSETP,
|
|
PSET,
|
|
CSETP,
|
|
R2P_IMM,
|
|
XMAD_IMM,
|
|
XMAD_CR,
|
|
XMAD_RC,
|
|
XMAD_RR,
|
|
};
|
|
|
|
enum class Type {
|
|
Trivial,
|
|
Arithmetic,
|
|
ArithmeticImmediate,
|
|
ArithmeticInteger,
|
|
ArithmeticIntegerImmediate,
|
|
ArithmeticHalf,
|
|
ArithmeticHalfImmediate,
|
|
Bfe,
|
|
Bfi,
|
|
Shift,
|
|
Ffma,
|
|
Hfma2,
|
|
Flow,
|
|
Synch,
|
|
Warp,
|
|
Memory,
|
|
Texture,
|
|
Image,
|
|
FloatSet,
|
|
FloatSetPredicate,
|
|
IntegerSet,
|
|
IntegerSetPredicate,
|
|
HalfSet,
|
|
HalfSetPredicate,
|
|
PredicateSetPredicate,
|
|
PredicateSetRegister,
|
|
RegisterSetPredicate,
|
|
Conversion,
|
|
Video,
|
|
Xmad,
|
|
Unknown,
|
|
};
|
|
|
|
/// Returns whether an opcode has an execution predicate field or not (ie, whether it can be
|
|
/// conditionally executed).
|
|
static bool IsPredicatedInstruction(Id opcode) {
|
|
// TODO(Subv): Add the rest of unpredicated instructions.
|
|
return opcode != Id::SSY && opcode != Id::PBK;
|
|
}
|
|
|
|
class Matcher {
|
|
public:
|
|
Matcher(const char* const name, u16 mask, u16 expected, OpCode::Id id, OpCode::Type type)
|
|
: name{name}, mask{mask}, expected{expected}, id{id}, type{type} {}
|
|
|
|
const char* GetName() const {
|
|
return name;
|
|
}
|
|
|
|
u16 GetMask() const {
|
|
return mask;
|
|
}
|
|
|
|
Id GetId() const {
|
|
return id;
|
|
}
|
|
|
|
Type GetType() const {
|
|
return type;
|
|
}
|
|
|
|
/**
|
|
* Tests to see if the given instruction is the instruction this matcher represents.
|
|
* @param instruction The instruction to test
|
|
* @returns true if the given instruction matches.
|
|
*/
|
|
bool Matches(u16 instruction) const {
|
|
return (instruction & mask) == expected;
|
|
}
|
|
|
|
private:
|
|
const char* name;
|
|
u16 mask;
|
|
u16 expected;
|
|
Id id;
|
|
Type type;
|
|
};
|
|
|
|
static std::optional<std::reference_wrapper<const Matcher>> Decode(Instruction instr) {
|
|
static const auto table{GetDecodeTable()};
|
|
|
|
const auto matches_instruction = [instr](const auto& matcher) {
|
|
return matcher.Matches(static_cast<u16>(instr.opcode));
|
|
};
|
|
|
|
auto iter = std::find_if(table.begin(), table.end(), matches_instruction);
|
|
return iter != table.end() ? std::optional<std::reference_wrapper<const Matcher>>(*iter)
|
|
: std::nullopt;
|
|
}
|
|
|
|
private:
|
|
struct Detail {
|
|
private:
|
|
static constexpr std::size_t opcode_bitsize = 16;
|
|
|
|
/**
|
|
* Generates the mask and the expected value after masking from a given bitstring.
|
|
* A '0' in a bitstring indicates that a zero must be present at that bit position.
|
|
* A '1' in a bitstring indicates that a one must be present at that bit position.
|
|
*/
|
|
static auto GetMaskAndExpect(const char* const bitstring) {
|
|
u16 mask = 0, expect = 0;
|
|
for (std::size_t i = 0; i < opcode_bitsize; i++) {
|
|
const std::size_t bit_position = opcode_bitsize - i - 1;
|
|
switch (bitstring[i]) {
|
|
case '0':
|
|
mask |= 1 << bit_position;
|
|
break;
|
|
case '1':
|
|
expect |= 1 << bit_position;
|
|
mask |= 1 << bit_position;
|
|
break;
|
|
default:
|
|
// Ignore
|
|
break;
|
|
}
|
|
}
|
|
return std::make_tuple(mask, expect);
|
|
}
|
|
|
|
public:
|
|
/// Creates a matcher that can match and parse instructions based on bitstring.
|
|
static auto GetMatcher(const char* const bitstring, OpCode::Id op, OpCode::Type type,
|
|
const char* const name) {
|
|
const auto mask_expect = GetMaskAndExpect(bitstring);
|
|
return Matcher(name, std::get<0>(mask_expect), std::get<1>(mask_expect), op, type);
|
|
}
|
|
};
|
|
|
|
static std::vector<Matcher> GetDecodeTable() {
|
|
std::vector<Matcher> table = {
|
|
#define INST(bitstring, op, type, name) Detail::GetMatcher(bitstring, op, type, name)
|
|
INST("111000110011----", Id::KIL, Type::Flow, "KIL"),
|
|
INST("111000101001----", Id::SSY, Type::Flow, "SSY"),
|
|
INST("111000101010----", Id::PBK, Type::Flow, "PBK"),
|
|
INST("111000100100----", Id::BRA, Type::Flow, "BRA"),
|
|
INST("111000100101----", Id::BRX, Type::Flow, "BRX"),
|
|
INST("1111000011111---", Id::SYNC, Type::Flow, "SYNC"),
|
|
INST("111000110100---", Id::BRK, Type::Flow, "BRK"),
|
|
INST("111000110000----", Id::EXIT, Type::Flow, "EXIT"),
|
|
INST("1111000011110---", Id::DEPBAR, Type::Synch, "DEPBAR"),
|
|
INST("0101000011011---", Id::VOTE, Type::Warp, "VOTE"),
|
|
INST("1110111111011---", Id::LD_A, Type::Memory, "LD_A"),
|
|
INST("1110111101001---", Id::LD_S, Type::Memory, "LD_S"),
|
|
INST("1110111101000---", Id::LD_L, Type::Memory, "LD_L"),
|
|
INST("1110111110010---", Id::LD_C, Type::Memory, "LD_C"),
|
|
INST("100-------------", Id::LD, Type::Memory, "LD"),
|
|
INST("1110111011010---", Id::LDG, Type::Memory, "LDG"),
|
|
INST("1110111111110---", Id::ST_A, Type::Memory, "ST_A"),
|
|
INST("1110111101011---", Id::ST_S, Type::Memory, "ST_S"),
|
|
INST("1110111101010---", Id::ST_L, Type::Memory, "ST_L"),
|
|
INST("101-------------", Id::ST, Type::Memory, "ST"),
|
|
INST("1110111011011---", Id::STG, Type::Memory, "STG"),
|
|
INST("1110111110100---", Id::AL2P, Type::Memory, "AL2P"),
|
|
INST("110000----111---", Id::TEX, Type::Texture, "TEX"),
|
|
INST("1101111010111---", Id::TEX_B, Type::Texture, "TEX_B"),
|
|
INST("1101111101001---", Id::TXQ, Type::Texture, "TXQ"),
|
|
INST("1101111101010---", Id::TXQ_B, Type::Texture, "TXQ_B"),
|
|
INST("1101-00---------", Id::TEXS, Type::Texture, "TEXS"),
|
|
INST("11011100--11----", Id::TLD, Type::Texture, "TLD"),
|
|
INST("1101-01---------", Id::TLDS, Type::Texture, "TLDS"),
|
|
INST("110010----111---", Id::TLD4, Type::Texture, "TLD4"),
|
|
INST("1101111100------", Id::TLD4S, Type::Texture, "TLD4S"),
|
|
INST("110111110110----", Id::TMML_B, Type::Texture, "TMML_B"),
|
|
INST("1101111101011---", Id::TMML, Type::Texture, "TMML"),
|
|
INST("11101011001-----", Id::SUST, Type::Image, "SUST"),
|
|
INST("0101000010110---", Id::NOP, Type::Trivial, "NOP"),
|
|
INST("11100000--------", Id::IPA, Type::Trivial, "IPA"),
|
|
INST("1111101111100---", Id::OUT_R, Type::Trivial, "OUT_R"),
|
|
INST("1110111111010---", Id::ISBERD, Type::Trivial, "ISBERD"),
|
|
INST("01011111--------", Id::VMAD, Type::Video, "VMAD"),
|
|
INST("0101000011110---", Id::VSETP, Type::Video, "VSETP"),
|
|
INST("0011001-1-------", Id::FFMA_IMM, Type::Ffma, "FFMA_IMM"),
|
|
INST("010010011-------", Id::FFMA_CR, Type::Ffma, "FFMA_CR"),
|
|
INST("010100011-------", Id::FFMA_RC, Type::Ffma, "FFMA_RC"),
|
|
INST("010110011-------", Id::FFMA_RR, Type::Ffma, "FFMA_RR"),
|
|
INST("0100110001011---", Id::FADD_C, Type::Arithmetic, "FADD_C"),
|
|
INST("0101110001011---", Id::FADD_R, Type::Arithmetic, "FADD_R"),
|
|
INST("0011100-01011---", Id::FADD_IMM, Type::Arithmetic, "FADD_IMM"),
|
|
INST("000010----------", Id::FADD32I, Type::ArithmeticImmediate, "FADD32I"),
|
|
INST("0100110001101---", Id::FMUL_C, Type::Arithmetic, "FMUL_C"),
|
|
INST("0101110001101---", Id::FMUL_R, Type::Arithmetic, "FMUL_R"),
|
|
INST("0011100-01101---", Id::FMUL_IMM, Type::Arithmetic, "FMUL_IMM"),
|
|
INST("00011110--------", Id::FMUL32_IMM, Type::ArithmeticImmediate, "FMUL32_IMM"),
|
|
INST("0100110000010---", Id::IADD_C, Type::ArithmeticInteger, "IADD_C"),
|
|
INST("0101110000010---", Id::IADD_R, Type::ArithmeticInteger, "IADD_R"),
|
|
INST("0011100-00010---", Id::IADD_IMM, Type::ArithmeticInteger, "IADD_IMM"),
|
|
INST("010011001100----", Id::IADD3_C, Type::ArithmeticInteger, "IADD3_C"),
|
|
INST("010111001100----", Id::IADD3_R, Type::ArithmeticInteger, "IADD3_R"),
|
|
INST("0011100-1100----", Id::IADD3_IMM, Type::ArithmeticInteger, "IADD3_IMM"),
|
|
INST("0001110---------", Id::IADD32I, Type::ArithmeticIntegerImmediate, "IADD32I"),
|
|
INST("0100110000011---", Id::ISCADD_C, Type::ArithmeticInteger, "ISCADD_C"),
|
|
INST("0101110000011---", Id::ISCADD_R, Type::ArithmeticInteger, "ISCADD_R"),
|
|
INST("0011100-00011---", Id::ISCADD_IMM, Type::ArithmeticInteger, "ISCADD_IMM"),
|
|
INST("0100110000001---", Id::POPC_C, Type::ArithmeticInteger, "POPC_C"),
|
|
INST("0101110000001---", Id::POPC_R, Type::ArithmeticInteger, "POPC_R"),
|
|
INST("0011100-00001---", Id::POPC_IMM, Type::ArithmeticInteger, "POPC_IMM"),
|
|
INST("0100110010100---", Id::SEL_C, Type::ArithmeticInteger, "SEL_C"),
|
|
INST("0101110010100---", Id::SEL_R, Type::ArithmeticInteger, "SEL_R"),
|
|
INST("0011100-10100---", Id::SEL_IMM, Type::ArithmeticInteger, "SEL_IMM"),
|
|
INST("0101101111011---", Id::LEA_R2, Type::ArithmeticInteger, "LEA_R2"),
|
|
INST("0101101111010---", Id::LEA_R1, Type::ArithmeticInteger, "LEA_R1"),
|
|
INST("001101101101----", Id::LEA_IMM, Type::ArithmeticInteger, "LEA_IMM"),
|
|
INST("010010111101----", Id::LEA_RZ, Type::ArithmeticInteger, "LEA_RZ"),
|
|
INST("00011000--------", Id::LEA_HI, Type::ArithmeticInteger, "LEA_HI"),
|
|
INST("0111101-1-------", Id::HADD2_C, Type::ArithmeticHalf, "HADD2_C"),
|
|
INST("0101110100010---", Id::HADD2_R, Type::ArithmeticHalf, "HADD2_R"),
|
|
INST("0111101-0-------", Id::HADD2_IMM, Type::ArithmeticHalfImmediate, "HADD2_IMM"),
|
|
INST("0111100-1-------", Id::HMUL2_C, Type::ArithmeticHalf, "HMUL2_C"),
|
|
INST("0101110100001---", Id::HMUL2_R, Type::ArithmeticHalf, "HMUL2_R"),
|
|
INST("0111100-0-------", Id::HMUL2_IMM, Type::ArithmeticHalfImmediate, "HMUL2_IMM"),
|
|
INST("01110---1-------", Id::HFMA2_CR, Type::Hfma2, "HFMA2_CR"),
|
|
INST("01100---1-------", Id::HFMA2_RC, Type::Hfma2, "HFMA2_RC"),
|
|
INST("0101110100000---", Id::HFMA2_RR, Type::Hfma2, "HFMA2_RR"),
|
|
INST("01110---0-------", Id::HFMA2_IMM_R, Type::Hfma2, "HFMA2_R_IMM"),
|
|
INST("0111111-1-------", Id::HSETP2_C, Type::HalfSetPredicate, "HSETP2_C"),
|
|
INST("0101110100100---", Id::HSETP2_R, Type::HalfSetPredicate, "HSETP2_R"),
|
|
INST("0111111-0-------", Id::HSETP2_IMM, Type::HalfSetPredicate, "HSETP2_IMM"),
|
|
INST("0101110100011---", Id::HSET2_R, Type::HalfSet, "HSET2_R"),
|
|
INST("0101000010000---", Id::MUFU, Type::Arithmetic, "MUFU"),
|
|
INST("0100110010010---", Id::RRO_C, Type::Arithmetic, "RRO_C"),
|
|
INST("0101110010010---", Id::RRO_R, Type::Arithmetic, "RRO_R"),
|
|
INST("0011100-10010---", Id::RRO_IMM, Type::Arithmetic, "RRO_IMM"),
|
|
INST("0100110010101---", Id::F2F_C, Type::Conversion, "F2F_C"),
|
|
INST("0101110010101---", Id::F2F_R, Type::Conversion, "F2F_R"),
|
|
INST("0011100-10101---", Id::F2F_IMM, Type::Conversion, "F2F_IMM"),
|
|
INST("0100110010110---", Id::F2I_C, Type::Conversion, "F2I_C"),
|
|
INST("0101110010110---", Id::F2I_R, Type::Conversion, "F2I_R"),
|
|
INST("0011100-10110---", Id::F2I_IMM, Type::Conversion, "F2I_IMM"),
|
|
INST("0100110010011---", Id::MOV_C, Type::Arithmetic, "MOV_C"),
|
|
INST("0101110010011---", Id::MOV_R, Type::Arithmetic, "MOV_R"),
|
|
INST("0011100-10011---", Id::MOV_IMM, Type::Arithmetic, "MOV_IMM"),
|
|
INST("1111000011001---", Id::MOV_SYS, Type::Trivial, "MOV_SYS"),
|
|
INST("000000010000----", Id::MOV32_IMM, Type::ArithmeticImmediate, "MOV32_IMM"),
|
|
INST("0100110001100---", Id::FMNMX_C, Type::Arithmetic, "FMNMX_C"),
|
|
INST("0101110001100---", Id::FMNMX_R, Type::Arithmetic, "FMNMX_R"),
|
|
INST("0011100-01100---", Id::FMNMX_IMM, Type::Arithmetic, "FMNMX_IMM"),
|
|
INST("0100110000100---", Id::IMNMX_C, Type::ArithmeticInteger, "IMNMX_C"),
|
|
INST("0101110000100---", Id::IMNMX_R, Type::ArithmeticInteger, "IMNMX_R"),
|
|
INST("0011100-00100---", Id::IMNMX_IMM, Type::ArithmeticInteger, "IMNMX_IMM"),
|
|
INST("0100110000000---", Id::BFE_C, Type::Bfe, "BFE_C"),
|
|
INST("0101110000000---", Id::BFE_R, Type::Bfe, "BFE_R"),
|
|
INST("0011100-00000---", Id::BFE_IMM, Type::Bfe, "BFE_IMM"),
|
|
INST("0011011-11110---", Id::BFI_IMM_R, Type::Bfi, "BFI_IMM_R"),
|
|
INST("0100110001000---", Id::LOP_C, Type::ArithmeticInteger, "LOP_C"),
|
|
INST("0101110001000---", Id::LOP_R, Type::ArithmeticInteger, "LOP_R"),
|
|
INST("0011100-01000---", Id::LOP_IMM, Type::ArithmeticInteger, "LOP_IMM"),
|
|
INST("000001----------", Id::LOP32I, Type::ArithmeticIntegerImmediate, "LOP32I"),
|
|
INST("0000001---------", Id::LOP3_C, Type::ArithmeticInteger, "LOP3_C"),
|
|
INST("0101101111100---", Id::LOP3_R, Type::ArithmeticInteger, "LOP3_R"),
|
|
INST("0011110---------", Id::LOP3_IMM, Type::ArithmeticInteger, "LOP3_IMM"),
|
|
INST("0100110001001---", Id::SHL_C, Type::Shift, "SHL_C"),
|
|
INST("0101110001001---", Id::SHL_R, Type::Shift, "SHL_R"),
|
|
INST("0011100-01001---", Id::SHL_IMM, Type::Shift, "SHL_IMM"),
|
|
INST("0100110000101---", Id::SHR_C, Type::Shift, "SHR_C"),
|
|
INST("0101110000101---", Id::SHR_R, Type::Shift, "SHR_R"),
|
|
INST("0011100-00101---", Id::SHR_IMM, Type::Shift, "SHR_IMM"),
|
|
INST("0100110011100---", Id::I2I_C, Type::Conversion, "I2I_C"),
|
|
INST("0101110011100---", Id::I2I_R, Type::Conversion, "I2I_R"),
|
|
INST("0011101-11100---", Id::I2I_IMM, Type::Conversion, "I2I_IMM"),
|
|
INST("0100110010111---", Id::I2F_C, Type::Conversion, "I2F_C"),
|
|
INST("0101110010111---", Id::I2F_R, Type::Conversion, "I2F_R"),
|
|
INST("0011100-10111---", Id::I2F_IMM, Type::Conversion, "I2F_IMM"),
|
|
INST("01011000--------", Id::FSET_R, Type::FloatSet, "FSET_R"),
|
|
INST("0100100---------", Id::FSET_C, Type::FloatSet, "FSET_C"),
|
|
INST("0011000---------", Id::FSET_IMM, Type::FloatSet, "FSET_IMM"),
|
|
INST("010010111011----", Id::FSETP_C, Type::FloatSetPredicate, "FSETP_C"),
|
|
INST("010110111011----", Id::FSETP_R, Type::FloatSetPredicate, "FSETP_R"),
|
|
INST("0011011-1011----", Id::FSETP_IMM, Type::FloatSetPredicate, "FSETP_IMM"),
|
|
INST("010010110110----", Id::ISETP_C, Type::IntegerSetPredicate, "ISETP_C"),
|
|
INST("010110110110----", Id::ISETP_R, Type::IntegerSetPredicate, "ISETP_R"),
|
|
INST("0011011-0110----", Id::ISETP_IMM, Type::IntegerSetPredicate, "ISETP_IMM"),
|
|
INST("010110110101----", Id::ISET_R, Type::IntegerSet, "ISET_R"),
|
|
INST("010010110101----", Id::ISET_C, Type::IntegerSet, "ISET_C"),
|
|
INST("0011011-0101----", Id::ISET_IMM, Type::IntegerSet, "ISET_IMM"),
|
|
INST("0101000010001---", Id::PSET, Type::PredicateSetRegister, "PSET"),
|
|
INST("0101000010010---", Id::PSETP, Type::PredicateSetPredicate, "PSETP"),
|
|
INST("010100001010----", Id::CSETP, Type::PredicateSetPredicate, "CSETP"),
|
|
INST("0011100-11110---", Id::R2P_IMM, Type::RegisterSetPredicate, "R2P_IMM"),
|
|
INST("0011011-00------", Id::XMAD_IMM, Type::Xmad, "XMAD_IMM"),
|
|
INST("0100111---------", Id::XMAD_CR, Type::Xmad, "XMAD_CR"),
|
|
INST("010100010-------", Id::XMAD_RC, Type::Xmad, "XMAD_RC"),
|
|
INST("0101101100------", Id::XMAD_RR, Type::Xmad, "XMAD_RR"),
|
|
};
|
|
#undef INST
|
|
std::stable_sort(table.begin(), table.end(), [](const auto& a, const auto& b) {
|
|
// If a matcher has more bits in its mask it is more specific, so it
|
|
// should come first.
|
|
return std::bitset<16>(a.GetMask()).count() > std::bitset<16>(b.GetMask()).count();
|
|
});
|
|
|
|
return table;
|
|
}
|
|
};
|
|
|
|
} // namespace Tegra::Shader
|