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ab65fde9f4
Add asserts for compute shader dispatching, transform feedback being enabled and alpha testing. These have in common that they'll probably break rendering without logging.
56 lines
1.6 KiB
C++
56 lines
1.6 KiB
C++
// Copyright 2018 yuzu Emulator Project
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// Licensed under GPLv2 or any later version
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// Refer to the license.txt file included.
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#pragma once
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#include <array>
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#include "common/assert.h"
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#include "common/bit_field.h"
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#include "common/common_funcs.h"
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#include "common/common_types.h"
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namespace Tegra::Engines {
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#define MAXWELL_COMPUTE_REG_INDEX(field_name) \
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(offsetof(Tegra::Engines::MaxwellCompute::Regs, field_name) / sizeof(u32))
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class MaxwellCompute final {
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public:
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MaxwellCompute() = default;
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~MaxwellCompute() = default;
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struct Regs {
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static constexpr std::size_t NUM_REGS = 0xCF8;
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union {
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struct {
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INSERT_PADDING_WORDS(0x281);
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union {
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u32 compute_end;
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BitField<0, 1, u32> unknown;
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} compute;
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INSERT_PADDING_WORDS(0xA76);
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};
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std::array<u32, NUM_REGS> reg_array;
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};
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} regs{};
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static_assert(sizeof(Regs) == Regs::NUM_REGS * sizeof(u32),
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"MaxwellCompute Regs has wrong size");
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/// Write the value to the register identified by method.
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void WriteReg(u32 method, u32 value);
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};
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#define ASSERT_REG_POSITION(field_name, position) \
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static_assert(offsetof(MaxwellCompute::Regs, field_name) == position * 4, \
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"Field " #field_name " has invalid position")
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ASSERT_REG_POSITION(compute, 0x281);
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#undef ASSERT_REG_POSITION
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} // namespace Tegra::Engines
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